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Elad0708's avatar
Elad0708
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2 years ago

DPX4 and DPx8 PHY

Hello, I am trying to build a PHY for DisplayPort 5.4GHz design we have. I am trying to set Dp-PHY with 4-lanes and 8-lanes, I encountered couple of issues during the process: first how can I conf...
Fpga Devkit
Elad0708's avatar
Elad0708
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2 years ago

Hi Aaron,

It is a little bit confusing; the question isn't only about DP. The question is about FPGA serdes regardless of DP. It is not DisplayPort by priority like the old spec iDP.

Can we get this serdes configuration:

  • Non-DP,

  • 8 lanes single reference clock for all,

  • rate 5.4G similar to DP,

  • VSPE per lane similar to DP,

  • Max skew between all lanes 1000 pS

The important thing for us is a single clock for all 8 lanes.

Regards,

Elad Rotem

  • zhenruan's avatar
    zhenruan
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    2 years ago

    Hi Elad,

    You can copy the 4-channel Transceiver Native PHY TX IP that generated for the DisplayPort example design (the rate is set to 5.4G) and modify the channel number from 4 to 8.

    Regards,

    Aaron