Hello,I am trying to build a PHY for DisplayPort 5.4GHz design we have. I am trying to set Dp-PHY with 4-lanes and 8-lanes, I encountered couple of issues during the process:first how can I configure PHY from the IP catalog? I don't see that the dp protocol is in the PHY selection, while using direct PHY configuration.If I select the DisplayPort IP (PHY+Bitec decoder), I see that it only supports DP 4lanes. Can I configure the DP PHY to be 8 lanes?I will appreciate your help on this subject.Best Regards,Elad Rotem

Hi Elad,Please instance the DisplayPort Intel FPGA IP directly. You can generate the DisplayPort Example design after the IP generation. The Transceiver Native PHY Intel FPGA IP is included. The DisplayPort Intel FPGA IP can be set to 1,2,4 lane per the DisplayPort protocol. If the design needs 8 lanes please instance the DisplayPort Intel FPGA IP twice. Regards,Aaron

Appreciate your help on this! So, I follow your instructions and the project finish synthesis. Two question I have: 1. Since I want to create 8-lanes and not two channels of DisplayPort, I created two instances of PHY. Both PHY's drive 'gxb_tx_clkout' so which one I should use? The DisplayPort controller should work only with one recovered clock. 2. Also, the analog parameters (vod & emp) disturbed me, since DisplayPort controller will need to check this two PHYs separately. Can't I configure this one instance of PHY ('tx_phy_top' in the example design) to work with 8 lanes? Best Regards,Elad Rotem

Hi Elad,You can't instance one 8-channel Transceiver Native PHY to work with 2 HDMI interface (HDMI source/HDMI sink). The HDMI source/sink doesn't support the lane number exceeding 4. As the design needs 8 lanes DisplayPort, you can divide it into two groups. Each group works separately. One 4-lane DP sink IP needs one 4-channel Transceiver Native PHY RX IP. One 4-lane DP source IP needs one 4-channel Transceiver Native PHY TX IP.Regards,Aaron

Hi Aaron,I need to correct my initial question. I require an 8-lane DP Tx; there's no need for RX lanes since these differential lines are directly connected to the LCD panel.Essentially, my question pertains more to the 'gxb_tx_clkout' (link layer clock). We only need one clock for the control layer, not two from each PHY instantiation.Regards,Elad

Hi Elad,The design requires 8-lane DP Tx; You must set them into 2 interfaces. Each works at the tx-only mode and has a 4-lane DP source and a 4-channel Transceiver Native PHY TX IP. It also needs a AUX channel for the link training. That is defined in the DisplayPort protocol. The Intel DisplayPort IP just conforms the DisplayPort Standard. Please refer to the DisplayPort spec for more information. That also means there are two gxb_tx_clkout clocks in the design. You can't use one gxb_tx_clkout clock for the 8 channel PHY. Four channels form an HDMI interface that works together independently of the other four channels. Regards,Aaron

DPX4 and DPx8 PHY | Altera Community

18 Replies

HelenMa
New Contributor
1 year ago
Hi Elad,
No, your understanding is wrong.
1. Currently Agilex7 F-tile transceiver IP can't be modified for DP application, it's only available for DP 4lanes. Please do not develop your DPx8 prject using Agilex7.
2. Arria10/Stratix10 transceiver IP can be modified in the transceiver IP GUI. So you can develop your DPx8 project using Arria10/Stratix10.
3. Arria10/Stratix10 transceiver is different from Agilex7. You can't integrate it into Agilex7 design.
Best Regards,
Helen
- Elad0708
  New Contributor
  1 year ago
  Hi Helen,
  Thank you for your support.
  Best Regards,
  Elad Rotem
WZ2
Frequent Contributor
1 year ago
Hi there,

I wanted to check if you have any further questions or concerns. If not, I will go ahead and mark this issue as resolved.

Additionally, we would greatly appreciate it if you could take a moment to fill out our survey. Your feedback is valuable to us and helps us improve our support quality.

Thank you for your time and cooperation.

Best regards,
WZ

Forum Discussion

DPX4 and DPx8 PHY

18 Replies

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