New Contributor
New ContributorAppreciate your help on this!
So, I follow your instructions and the project finish synthesis. Two question I have:
1. Since I want to create 8-lanes and not two channels of DisplayPort, I created two instances of PHY. Both PHY's drive 'gxb_tx_clkout' so which one I should use? The DisplayPort controller should work only with one recovered clock.
2. Also, the analog parameters (vod & emp) disturbed me, since DisplayPort controller will need to check this two PHYs separately.
Can't I configure this one instance of PHY ('tx_phy_top' in the example design) to work with 8 lanes?
Best Regards,
Elad Rotem
New ContributorHi Elad,
You can't instance one 8-channel Transceiver Native PHY to work with 2 HDMI interface (HDMI source/HDMI sink). The HDMI source/sink doesn't support the lane number exceeding 4.
As the design needs 8 lanes DisplayPort, you can divide it into two groups. Each group works separately.
One 4-lane DP sink IP needs one 4-channel Transceiver Native PHY RX IP.
One 4-lane DP source IP needs one 4-channel Transceiver Native PHY TX IP.
Regards,
Aaron
