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Elad0708's avatar
Elad0708
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2 years ago

DPX4 and DPx8 PHY

Hello, I am trying to build a PHY for DisplayPort 5.4GHz design we have. I am trying to set Dp-PHY with 4-lanes and 8-lanes, I encountered couple of issues during the process: first how can I conf...
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Elad0708's avatar
Elad0708
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2 years ago

Appreciate your help on this!

So, I follow your instructions and the project finish synthesis. Two question I have:

1. Since I want to create 8-lanes and not two channels of DisplayPort, I created two instances of PHY. Both PHY's drive 'gxb_tx_clkout' so which one I should use? The DisplayPort controller should work only with one recovered clock.

2. Also, the analog parameters (vod & emp) disturbed me, since DisplayPort controller will need to check this two PHYs separately.

Can't I configure this one instance of PHY ('tx_phy_top' in the example design) to work with 8 lanes?

Best Regards,

Elad Rotem

zhenruan's avatar
zhenruan
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2 years ago

Hi Elad,

You can't instance one 8-channel Transceiver Native PHY to work with 2 HDMI interface (HDMI source/HDMI sink). The HDMI source/sink doesn't support the lane number exceeding 4.

As the design needs 8 lanes DisplayPort, you can divide it into two groups. Each group works separately.

One 4-lane DP sink IP needs one 4-channel Transceiver Native PHY RX IP.

One 4-lane DP source IP needs one 4-channel Transceiver Native PHY TX IP.

Regards,

Aaron