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Agilex 5 SDI 148.5 and 148.35 MHz refclks
I'm working on a design for the Agilex 5 that is going to need to be able to switch between integer and fractional framerates, and I'm trying to figure out and understand the clocking structure involved. In the GTS SDI II IP User Guide, there is a set of parameters for "Transceiver reference clock frequency" and "Dynamic TX clock switching" under the category "Transceiver Options", however I don't see these parameters in Quartus. Is there somewhere else that I can enable this option to have the two different reference clock frequencies? Do I need this enabled, or is there some other way that I can switch between the two frequencies? In addition, what does the clocking structure look like to do this? Is there a way to provide 148.5 MHz to the board and then generate the 148.35 from a PLL to be multiplexed? Or do I need to provide both clock frequencies separately? If I need to provide both clock frequencies separately, what pins can I use for the 148.35 MHz reference clock? The two differential pairs of reference clocks for the GTS bank are already being used for the System PLL reference clock and the 148.5 MHz. Any help with these questions would be greatly appreciated.
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yuriah726
21 days ago Place IP & Transceiver
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Agilex‑7 F‑Tile Dynamic Reconfiguration Conflict Between HDMI and SDI RX
Hello, I am working on a design targeting an Agilex‑7 device (AGFB014R24C2I2V) using Quartus Prime Pro 23.2. The design includes two video RX interfaces on the same F‑Tile, both configured as input-only: HDMI (TMDS only) SDI‑12G Both IP cores use dynamic reconfiguration to adapt the transceiver to the detected input frequency: HDMI: Mixed single-rate PHY (63 profiles) SDI: Multi-rate PHY (4 profiles) Since both IPs are located in the same F‑Tile, they share: A single dynamic reconfiguration block (through the arbiter from the provided IP example) The same System PLL Observed Behavior When only one RX IP is instantiated (either HDMI or SDI), the link comes up correctly and video is received as expected. When both RX IPs are instantiated simultaneously: HDMI link initializes and operates correctly. SDI PHY fails to lock to the input signal. Debug Observations Using SignalTap on the dynamic reconfiguration interface: The SDI reconfiguration state machine cycles through all profiles. Each reconfiguration completes successfully (no errors reported). Despite this, the SDI RX never achieves lock. Suspected Cause This appears to be potentially related to a resource conflict or incorrect sharing configuration within the F‑Tile, possibly due to QSF assignments or transceiver resource allocation. However, the exact root cause is unclear, and I may be overlooking a configuration requirement for: Shared dynamic reconfiguration usage Multi‑client arbitration F‑Tile resource partitioning Additional Information Below are the QSF assignments used to configure the dynamic reconfiguration IP. For brevity, only the first and last HDMI profiles (out of 63) are included. # Configure global assignments for SytemPLL set_location_assignment PIN_BH8 -to REFCLKIN_HDMI_13A -comment "Pin Function Name is REFCLK_FGTR13A_Q0_RX_CH0P" set_location_assignment PIN_BJ7 -to "REFCLKIN_HDMI_13A(n)" set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to REFCLKIN_HDMI_13A -entity iWave_HelloWorld set_location_assignment PIN_BP8 -to REFCLKIN_100M_13A -comment "Pin Function Name is REFCLK_FGTR13A_Q1_RX_CH3P" set_location_assignment PIN_BN7 -to "REFCLKIN_100M_13A(n)" set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to REFCLKIN_100M_13A -entity iWave_HelloWorld set_location_assignment PIN_CJ7 -to REFCLKIN_148M5_13A -comment "Pin Function Name is REFCLK_FGTR13A_Q3_RX_CH6P" set_location_assignment PIN_CH8 -to "REFCLKIN_148M5_13A(n)" set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to REFCLKIN_148M5_13A -entity iWave_HelloWorld set_instance_assignment -name IP_TILE_ASSIGNMENT Z1577B_X339_Y0_N0 -to U_VideoIn|U_MGT_SUPPORT.U_PLL|systemclk_f_0 -entity iWave_HelloWorld set_instance_assignment -name IP_BB_LOCATION FGT_REFCLK_0 -to U_VideoIn|U_MGT_SUPPORT.U_PLL|systemclk_f_0|x_hip|gen_refclk_fgt_bb_[0].enabled.inst -entity iWave_HelloWorld -comment "Device Location is x_z1577b|ux_refclk|ux_refclk0" set_instance_assignment -name IP_BB_LOCATION FGT_REFCLK_3 -to U_VideoIn|U_MGT_SUPPORT.U_PLL|systemclk_f_0|x_hip|gen_refclk_fgt_bb_[3].enabled.inst -entity iWave_HelloWorld -comment "Device Location is x_z1577b|ux_refclk|ux_refclk3" set_instance_assignment -name IP_BB_LOCATION FGT_REFCLK_6 -to U_VideoIn|U_MGT_SUPPORT.U_PLL|systemclk_f_0|x_hip|gen_refclk_fgt_bb_[6].enabled.inst -entity iWave_HelloWorld -comment "Device Location is x_z1577b|ux_refclk|ux_refclk6" # Configure global assignments for dynamic reconfig set_instance_assignment -name IP_TILE_ASSIGNMENT Z1577B_X339_Y0_N0 -to U_VideoIn|U_MGT_SUPPORT.U_Reconfig|dr_f_0 -entity iWave_HelloWorld set_global_assignment -name IP_RECONFIG_GROUP_TYPE "MASTER_DR:INCLUSIVE" -entity iWave_HelloWorld # HDMI DR set_global_assignment -name IP_RECONFIG_GROUP_PARENT "MASTER_DR:VIDEOINPUT0_DR" -entity iWave_HelloWorld set_global_assignment -name IP_RECONFIG_GROUP_TYPE "VIDEOINPUT0_DR:EXCLUSIVE:SHARED_SIP:CLK_MASTER" -entity iWave_HelloWorld set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_RX_CLK_OUT1_DCM -to U_VideoIn|U_INPUT_0|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[0].perxcvr[0].peraib[0].rx_aib.x_bb_m_hdpldadapt_rx -entity iWave_HelloWorld set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON -to U_VideoIn|U_INPUT_0|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_0|rx_phy_12g set_instance_assignment -name IP_RECONFIG_GROUP_SHARED_SIP ON -to U_VideoIn|U_INPUT_0|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_0|rx_phy_12g set_instance_assignment -name IP_RECONFIG_GROUP VIDEOINPUT0_DR -to U_VideoIn|U_INPUT_0|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_0|rx_phy_12g -entity iWave_HelloWorld ... set_instance_assignment -name IP_RECONFIG_GROUP VIDEOINPUT0_DR -to U_VideoIn|U_INPUT_0|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_62|rx_phy_0p300g -entity iWave_HelloWorld set_instance_assignment -name IP_COLOCATE F_TILE -from U_VideoIn|U_MGT_SUPPORT.U_Reconfig|dr_f_0 -to U_VideoIn|U_INPUT_1|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_0|rx_phy_12g -entity iWave_HelloWorld ... set_instance_assignment -name IP_COLOCATE F_TILE -from U_VideoIn|U_MGT_SUPPORT.U_Reconfig|dr_f_0 -to U_VideoIn|U_INPUT_1|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_62|rx_phy_0p300g -entity iWave_HelloWorld set_instance_assignment -name IP_RECONFIG_ID 101 -to U_VideoIn|U_INPUT_1|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_0|rx_phy_12g -entity iWave_HelloWorld ... set_instance_assignment -name IP_RECONFIG_ID 163 -to U_VideoIn|U_INPUT_1|U_HDMI_TMDS.U1|U_HDMI|gxb_rx_inst|u_rx_phy_62|rx_phy_0p300g -entity iWave_HelloWorld # SDI DR set_global_assignment -name IP_RECONFIG_GROUP_PARENT "MASTER_DR:VIDEOINPUT1_DR" -entity iWave_HelloWorld set_global_assignment -name IP_RECONFIG_GROUP_TYPE "VIDEOINPUT1_DR:EXCLUSIVE:CLK_MASTER" -entity iWave_HelloWorld set_global_assignment -name IP_RECONFIG_GROUP_PARENT "VIDEOINPUT1_DR:U_VideoIn|U_INPUT_1|U_SDI.U3|U_SDI|sdi_mr_rx_sys_inst|rx_phy|rx_phy/RG_A_E" -entity iWave_HelloWorld set_instance_assignment -name IP_COLOCATE F_TILE -from U_VideoIn|U_MGT_SUPPORT.U_Reconfig|dr_f_0 -to U_VideoIn|U_INPUT_1|U_SDI.U3|U_SDI|sdi_mr_rx_sys_inst|rx_phy|rx_phy -entity iWave_HelloWorld set_instance_assignment -name IP_RECONFIG_ID 164 -to U_VideoIn|U_INPUT_1|U_SDI.U3|U_SDI|sdi_mr_rx_sys_inst|rx_phy|rx_phy set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_RX_CLK_OUT1_DCM -to U_VideoIn|U_INPUT_1|U_SDI.U3|U_SDI|sdi_mr_rx_sys_inst|rx_phy|rx_phy|U_base_profile|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].peraib[0].rx_aib.x_bb_m_hdpldadapt_rx -entity iWave_HelloWorld Generated Reconfiguration IDs After support logic generation, the IDs are correctly reflected: #define NUM_IP_INSTS 67 #define IWAVE_HELLOWORLD__U_VIDEOIN__U_INPUT_0__U_HDMI_TMDS__U1__U_HDMI__GXB_RX_INST__U_RX_PHY_0__RX_PHY_12G 101 ... #define IWAVE_HELLOWORLD__U_VIDEOIN__U_INPUT_0__U_HDMI_TMDS__U1__U_HDMI__GXB_RX_INST__U_RX_PHY_62__RX_PHY_0P300G 163 #define IWAVE_HELLOWORLD__U_VIDEOIN__U_INPUT_1__U_SDI__U3__U_SDI__SDI_MR_RX_SYS_INST__RX_PHY__RX_PHY__U_BASE_PROFILE__DIRECTPHY_F_0 164 #define IWAVE_HELLOWORLD__U_VIDEOIN__U_INPUT_1__U_SDI__U3__U_SDI__SDI_MR_RX_SYS_INST__RX_PHY__RX_PHY__U_SEC_PROFILE1__SEC_PROFILE_1 165 #define IWAVE_HELLOWORLD__U_VIDEOIN__U_INPUT_1__U_SDI__U3__U_SDI__SDI_MR_RX_SYS_INST__RX_PHY__RX_PHY__U_SEC_PROFILE2__SEC_PROFILE_2 166 #define IWAVE_HELLOWORLD__U_VIDEOIN__U_INPUT_1__U_SDI__U3__U_SDI__SDI_MR_RX_SYS_INST__RX_PHY__RX_PHY__U_SEC_PROFILE3__SEC_PROFILE_3 167 Any guidance on: Proper sharing of dynamic reconfiguration between multiple RX IPs on the same F‑Tile Known limitations or requirements for mixing HDMI (TMDS) and SDI PHYs QSF settings that could cause this behavior would be greatly appreciated. Thank you.
etienne_cf
27 days ago Place IP & Transceiver
81Views
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Is it possible to add on-screen display to the SDI output of an SDI II FPGA IP?
I'm considering SDI II FPGA IP. I plan to display on-screen text (text) on the SDI output of our product. I would like to add logic for text composition. Is SDI II FPGA IP compatible with this ?
yamasan
1 month ago Place IP & Transceiver
106Views
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2Comments
VVP vs VIP Performance
Hi altera, I would like to know if there's any performance as well as resource improvement on VVP compared to VIP. I am evaluating the possibility of porting an old project on C10 GX I6 grade which using scaler II,CSC II, mixer.. Thank you.
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JLee25
1 month ago Place IP & Transceiver
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VVP RAM Clk
Hello, I am using VVP Pixels In Parallel converter Lite Mode, convert from parallel pixels from 4 to 2. Configurations see below. All the connections are fine and no error messages on Platform Designer. But failed to pass synthesis for errors like, clock connection.. How can I debug this issue? The project is running on Quartus Pro 25.3.0. Thank you.
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JLee25
1 month ago Place IP & Transceiver
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MIPI CSI IP using M20K ram for 128 bits
I'm looking at the design assistant warnings for my project. And I see some weird usage by the mipi csi 2 core (Agilex 5 device, intel_mipi_csi2 v3.0.0). I'm greedy about my ram blocks, and I do not think it is reasonable for an IP core to use this for deskew. It's a problem because we use multiple mipi streams.. so it seems like a huge waste of M20Ks. Why arent they using MLABs? Example location: <my_system>|intel_mipi_csi2_0|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[2].gen_per_byte[1].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM <my_system>|intel_mipi_csi2_1|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[0].gen_per_byte[0].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM Any way to fix this? or a variant IP that fixes it? Thank you. Regards.
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maagnus0re
3 months ago Place IP & Transceiver
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Display port TX SST not working.
Hi, I am working on an existing project where Display Port Transmitter MST (multi stream) is already present and working. In the current version I just need to convert that transmitter into a Dispaly Port TX SST (single stream). The result is that, starting from the design example i got a version which works only up to 3840x2160 30Hz and does not at 3840x2160 60Hz. In both cases the training is completed and lane allocated adt 5.4GHz. Bun in tha case of 60 Hz I do not see any image. The Quartus Prime Pro used is 17.1.2 for Windows. I do not know where to check for debug more. Kind Regards, Paolo.
PMice
3 months ago Place IP & Transceiver
71Views
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Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
We are using a Stratix 10 L-Tile/H-Tile Transceiver Native PHY to implement a DisplayPort TX and RX. The transceiver is set as Basic (Enhanced PCS), TX/RX Duplex. The TX PMA is set as Non bonded, with 2 TX PLL clock inputs. One of the TX PLL clock inputs is driven by a fPLL and used for rates from 1.62G up to 13.5G. The other clock input is driven by two ATX PLLs (one working as Main PLL, the other as GXT Clock Buffer) and used for 20G rate. This works ok. The problem is that DisplayPort requires controlled skew between the 4 TX channels. That is, we need bonding for the 4 TX channels. If we set the TX PMA as "PMA only bonding" it seems we cannot have anymore multiple TX PLL clock inputs but just a single one. How can we use the Stratix 10 PHY to implement DisplayPort TX rates from 1.62G up to 20G with 4 bonded channels (= 4 lanes)?
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dncmrc1
5 months ago Place IP & Transceiver
170Views
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GTS SDI II IP Core...what is the tx_vid_clkout frequency
I'm using an Agelix 5 (the Altera development board) with Quartus Pro 25.3.1 w/patch 1.02. i'm trying to set-up the GTS SDI II IP Core (version 2.3.0) on the Main screen, the only configurable values are: Video Standard = HD-SDI Direction = Transmitter Insert payload ID = off SDI_II wrapper = Both BASE and PHY everything else is grayed out. I have connected the tx_pll_refclk to the 148.5MHz input. I do see the tx_pll_locked signal behave as expected and it does lock. the problem is when I look at the tx_vid_clkout signal its 58.3MHz. I expected it to be 74.25MHz. I'm somewhat confused as to whether tx_pll_refclk should be 148.5MHz or 74.25MHz, but if the 148.5 is wrong then I would have expected tx_vid_clkout to be twice, not a somewhat random value of 58.3MHz. when I reconfigured the IP core for 3G-SDI, the tx_vid_clkout frequency doubled to 116MHz. The doubling would be what I expected, but still a wrong frequency. i'm not sure what i'm setting wrong and why i'm getting a clkout of 58.3MHz
aucamera1
5 months ago Place IP & Transceiver
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How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew
Hi, We are implementing a 16-lane custom 1.0125 Gbps TX with F-tile PMA Direct PHY IP. The 16 lanes should be bonded together and they need to have a skew of less than 0.05 UI. However, we simulated the TX and found the serial output of each lane had skew of up to 11 ns, despite the fact that they had sychronized parallel input data. We have followed the suggested settings in user guide to enable system bonding, such as Number of Lanes=16, PMA Width=16, and Selected tx_clkout clock source=Bond Clock. For IP port connection, we use tx_clkout[0] as the source of all 16 tx_coreclkin. We also use it to clock all 16 parallel input data of TX in FPGA core fabric to make sure they are synchronized. Our IP Parameter and waveform is as attched. In testbench we feed parallel input data to all 16 lanes at the same time. We also assert TX PMA Interface Data Valid bit [38]. However, the serial output of each lane seems to start at different point of time, creating skew. Is this model behavior or actual hardware behavior? We tested on development board and our target sink is unable to lock to TX serial output as expected. Is there any way to eliminate the skew? Below is quartus version and our target board. Quartus Version : 25.3 Target Board : AGIC040R39A2E2VR0 Thanks wentsung
wentsung
6 months ago Place IP & Transceiver
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