New ContributorMIPI CSI IP using M20K ram for 128 bits
I'm looking at the design assistant warnings for my project. And I see some weird usage by the mipi csi 2 core (Agilex 5 device, intel_mipi_csi2 v3.0.0). I'm greedy about my ram blocks, and I do not think it is reasonable for an IP core to use this for deskew.
It's a problem because we use multiple mipi streams.. so it seems like a huge waste of M20Ks. Why arent they using MLABs?
Example location:
<my_system>|intel_mipi_csi2_0|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[2].gen_per_byte[1].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM
<my_system>|intel_mipi_csi2_1|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[0].gen_per_byte[0].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM
Any way to fix this? or a variant IP that fixes it? Thank you.
Regards.
Hi maagnus0re ,
I just try to understand which design are you refer to ? Is it from Design Example ? if yes , which version of Quartus you are using ?or this is your custom design of trying to add multiple mipi stream ?
Can you show me the whole complete log of the design assistant warning ?
If I understand correctly from your issue description, you are trying to use MLAB instead of M20k provided in MIPI CSI 2 IP, As far as I know the reason of using M20K RAM blocks for deskew FIFOs is because deskew across multiple lanes requires reliable, synchronous FIFO operation, and the IP core is designed to auto-generate these using M20Ks by default—not MLABs. There are no user-facing options or alternative IPs that allow use of MLABs for this function as of now.
Regards,
Wincent_Altera
