MIPI CSI IP using M20K ram for 128 bits

I'm looking at the design assistant warnings for my project. And I see some weird usage by the mipi csi 2 core (Agilex 5 device, intel_mipi_csi2 v3.0.0). I'm greedy about my ram blocks, and I do not think it is reasonable for an IP core to use this for deskew. 

It's a problem because we use multiple mipi streams.. so it seems like a huge waste of M20Ks. Why arent they using MLABs? 

Example location:

<my_system>|intel_mipi_csi2_0|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[2].gen_per_byte[1].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM

<my_system>|intel_mipi_csi2_1|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[0].gen_per_byte[0].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM

Any way to fix this? or a variant IP that fixes it? Thank you.

Regards.