mipi csi2 tx, upper limit of video width
Hi, I am using Quartus ver 26.1 PRO Edition and investigating the MIPI CSI-2 TX IP on Agilex 5 E. I generated the CSI-2 Example Design and am running a RTL simulation. To change the video width, I modified the setting of FRAME_WIDTH_PIXELS in cfg_pkg.sv. When FRAME_WIDTH_PIXELS = 3840, the operation is normal. However, when FRAME_WIDTH_PIXELS = 7680, tready goes low and the system stalls. Is there an upper limit for FRAME_WIDTH_PIXELS? The IP setting is follow:
Regarding MIPI CSI 2 TX
Hi, In my Project, I have to generate test pattern data and send it to MIPI CSI 2 via AXI stream, and MIPI CSI 2 will send the pixel data to link_0 of MIPI DPHY IP , but when i try to simulate the design(includes MIPI CSI 2 and MIPI DHPY IP interconnected), mipi_dphy_0/LINK0_CK_Stopstate is constantly high, I guess this signal is supposed to go low after T INT time, and also ready Singal from axi_stream is asserted low after being high for three clock cycles, i didn't understand why. Any help is appreciated.
Regarding the TX settings of MIPI CSI2 IP
In my Qsys project, I want to implement a function where the Test Pattern Generator IP sends the pattern to the MIPI CSI2 TX via an AXI stream. The MIPI CSI2 TX then sends the pixel data to link1 of the MIPI DPHE. After looping back, link0 of the MIPI DPHE sends the data to the MIPI CSI2 RX via the MIPI interface. However, strangely, the MIPI CSI2 TX axi stream ready signal remains low, and it doesn't process axi stream data from the TPG. The MIPI CSI2 TX settings are shown in the figure. What could be causing this phenomenon? Any help is appreciated.
