Agilex 3 MIPI D-PHY RX: Does it support P/N polarity inversion?

Hello Altera Support Team,

I am developing a 4-lane MIPI CSI-2 RAW10 camera receiver using the Agilex 3 FPGA and SoC C-Series Development Kit (DK-A3W135BM16AEA).

Before finalizing the camera adapter PCB design, I would like to confirm whether P/N polarity inversion is supported by the Agilex 3 MIPI D-PHY RX IP.

My questions are:

1. Does the MIPI D-PHY RX support P/N polarity inversion independently for each data lane (D0, D1, D2, and D3)?
2. Does the MIPI D-PHY RX support P/N polarity inversion on the clock lane?
3. If P/N polarity inversion is supported, does it work correctly in both High-Speed (HS) and Low-Power (LP) modes?
4. Is there a Quartus Prime IP parameter, pin assignment, or other supported configuration that enables P/N polarity inversion?
5. If P/N polarity inversion is not supported, must the camera and FPGA differential pairs always be connected P-to-P and N-to-N?
6. Could you provide an official documentation reference or confirmation from the MIPI D-PHY IP engineering team?

We have not connected or powered the camera yet. We would like to resolve this question before manufacturing or connecting the adapter PCB.

Thank you for your technical assistance.