MIPI CSI IP using M20K ram for 128 bits

Hi maagnus0re ​ ,

I just try to understand which design are you refer to ? Is it from Design Example ? if yes , which version of Quartus you are using ?

or this is your custom design of trying to add multiple mipi stream ?
Can you show me the whole complete log of the design assistant warning ?

If I understand correctly from your issue description, you are trying to use MLAB instead of M20k provided in MIPI CSI 2 IP, As far as I know the reason of using M20K RAM blocks for deskew FIFOs is because deskew across multiple lanes requires reliable, synchronous FIFO operation, and the IP core is designed to auto-generate these using M20Ks by default—not MLABs. There are no user-facing options or alternative IPs that allow use of MLABs for this function as of now.

Regards,
Wincent_Altera