Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted
Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file? A set of pin locations and IO standard settings for the AXE5 Eagle would be optimal, but any other dev kit would be helpful. According to the "GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs" (848477) page 29 under "Target Development Kit Tab" is says: "Target development kit option specifies the target development kit used to generate the project. Ensure the pin assignments in the .qsf file are appropriate." But it seems like this will only set the BOARD parameter in the resulting qsf, e.g. when using the Premium Development Kit it results in the following addtion to the qsf file: set_global_assignment -name BOARD "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1" which results in no location or IO standard settings in the qsf and I/O Assignment Warnings in the fitter report after the build: +-----------------------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; o_tx_serial_data[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; o_tx_serial_data_n[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_lowpwr ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_rstn ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; i_reconfig_clk ; Missing I/O standard ; ; i_rx_serial_data_n[0] ; Missing I/O standard ; ; i_rx_serial_data[0] ; Missing I/O standard ; ; i_clk_ref_p ; Missing I/O standard ; ; o_tx_serial_data[0] ; Missing location assignment ; ; o_tx_serial_data_n[0] ; Missing location assignment ; ; qsfp_lowpwr ; Missing location assignment ; ; qsfp_rstn ; Missing location assignment ; ; i_reconfig_clk ; Missing location assignment ; ; i_rx_serial_data_n[0] ; Missing location assignment ; ; i_rx_serial_data[0] ; Missing location assignment ; ; i_clk_ref_p ; Missing location assignment ; ; i_refclk2pll_p ; Missing location assignment ; +-----------------------+-----------------------------------------------------------------------------------------------+ Whenever I try to assign these myself I get errors like Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IPFLUXTOP_UXTOP_WRAP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 IPFLUXTOP_UXTOP_WRAP, which is within GTS Ethernet Hard IP ex_10G_intel_eth_gts_1000_6dyx4dq. or this or other type of layout or clocking type constraint errors: Error (11216): Output port "O_SYSPLL_C0" of "SM_HSSI_PLL_WRAP" cannot connect to PLD port "CLK" of "FF" for node "kr_dut|intel_eth_anlt_gts_0|ip_inst|sip_inst|u_intel_eth_anlt_gts_csr_top|u__intel_eth_anlt_gts_csr_avmm_arb|o_avmm_rdata[0]". It would be nice if I could obtain a set of correct and working pin assignment which actually results in a working sof file so I can try to understand what the actual constraints are. Is there a dev kit as described which the pin assignments are generated or provided or could anybody please provide a set of pin assignments for the above signals for a dev kit? Cheers!
Agilex 7 I Series Development Kit: External hardware access error when programming
I have a compiled design that I would like to test that implements Ethernet on F-Tile. When I try to program the FPGA with my bitstream, it stops and prompts me with the following errors: Would anyone know how to fix this or have insight on why this is happening?F-tile 10GBASE-R firecode FEC IP (Agilex 7)
Hi! We require to support 10GBASE-R clause 74 (firecode) FEC + PCS. This option isn't available in the Agile 7 F-Tile hard FEC IP. It is available for 25G rates, but we need it specifically for 10G. Our application doesn't require a MAC, in other rates we are to use PCS/MII mode It seems the only way forward is a soft firecode FEC + PCS, which would could connect to our FGT in PMA direct mode. Is this correct, and does altera provide an equivalent soft IP in order to support this configuration?
F-Tile Ethernet Hard IP Design Example - Testbench
I have a question regarding this Ftile Ethernet hard IP example Design. I am able to generate this example design for 400gbe. I am able to load this design (sof) to MA2700Kit. I was able to run tcl script and internal loopback test was successful. I was also able to run testbench basic_avl_tb_top.sv and VSIM run was successful. I have following questions and areas where I need help. At line 144 and 145 in basic_avl_tb_top.sv I can see that Tx outputs are assigned Rx input pins. I would like to understand reason for doing this? I mean shouldn’t the RX lines driven by tasks/function to simulate incoming packets over the ethernet link? I want to modify the testbench to simulate Receiving of a particular 98 byte ethernet frame, and check how mac segmented interface is behaving to communicate this frame; So i can write my custom RTL block to receive it properly. I need help developing tasks/function to simulate incoming packets over the ethernet link. Thank youF-tile-ethernet-hard-ip TX/RX MAC Segmented Client Interface
https://docs.altera.com/r/docs/683023/25.1.1/f-tile-ethernet-hard-ip-user-guide/tx-mac-segmented-client-interface "i_tx_mac_inframe" signal is explained as " Indicates valid data in each segment for specific rate. Along with the previous segment's inframe signal, this signal indicates the SOP and EOP location." i dont understand the underlined part of explanation. how does i_tx_mac_inframe indicates start of packer (SOP) and end of packet (EOP). can someone please elaborate on this with a couple of examples also another question is how to interpret i_tx_mac_data signals if i_tx_mac_valid == 1'b1 and i_tx_mac_inframe [15:0] == 16'h0 ?F-Tile xcvr placement on DK-DEV-AGF023FA
I have an Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF023F. I have 1 F-Tile working with PCIe Gen4x16, and want to use the second for 400Gb Ethernet. I have used the F-Tile channel placement tool, which results in a valid placement. See attached. I have been plagued with placer message such as the following. Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 400g block but the location only supports stream(s) [7, 11, 13, 14]. I have swapped bit orders and other trials, and they all lead to a similar error. Given the placement of the QSFPDD on the board, I need to used FGT Quads 2 and 3 I have also tried to use the 100G-4 F-Tile configuration, which move the FGT usage to Quad 1. And I result it the following error: Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 100g block but the location only supports stream(s) [1, 2, 3]. I have tried the example design, changing the device to the above board, but the build fails. Using Quartus 25.3.0 What is needed to move past these errors? Thanks, Ed.
Connecting Intel Agilex FPGA to DE1-SoC via Hub
Hello, I have an Intel Agilex FPGA with QSFP-DD 10 GbE PHY, a DE1-SoC board with 1 GbE PHY, and an Ethernet Hub 1 GbE. I want to connect the Agilex to the DE1-SoC through this hub. I understand the DE1-SoC only supports 1 GbE while the Agilex PHY is capable of 10 GbE. I would like to know the best way to communicate between these boards. Is it possible to configure the Agilex Ethernet IP and PHY to 1 GbE so it can communicate directly through the hub without a physical adapter? If not, would a media converter or adapter be needed to downspeed from 10 GbE to 1 GbE? Are there any recommended best practices for connecting an Agilex to a slower device like the DE1-SoC via Ethernet? Any guidance or experience would be greatly appreciated. Thank you!Can't generate F-Tile Ethernet Hard IP Design Example
When I try to generate an example design for the F-Tile Ethernet Hard IP or even the F-Tile Low Latency 100G Ethernet IP, the generating step gets stuck in a loop and will stay that way until I manually stop it in Task Manager. Has anyone else encountered this issue?
F-Tile Ethernet Hard IP (100G)
We are using the "F-Tile Ethernet Hard IP" (rev 15.0.0) in 100GE-4 + FEC mode in an Agilex 7 since >1 year, and it has worked fine when we build it with Quartus 24.2, but now after upgrading to Quartus 25.3.1 (patch 1.02) our 100G Ethernet switch no longer gets a link to the FPGA. I have re-generated the"F-Tile Ethernet Hard IP" (rev 20.1.0) in Q25.3.1 with exactly the same settings (not using 'Advanced mode') as we had when generating it in Q24.2 One difference I see in the *.ip files is this: rev 15.0.0: CUSTOM_RATE_GUI 25.78125 rev 20.1.0: CUSTOM_RATE_GUI 10.3125 These settings are not visible when not running 'Advanced mode' Is there anyone else that has seen problems with this IP after upgrading to Q25.3.1? A side note, we are also using the IP in 400GE-4 mode, and that works fine both in Q24.2 and Q25.3.1
