Agilex 5 GTS Supported Protocols
Hi Altera/Community, I’m trying to better understand the protocols supported by the Agilex 5 GTS transceivers. In the user guide, it mentions that the supported protocol is 10GBase-LR. I wanted to confirm: is 10GBase-R the underlying protocol used before the optical module? Also, does this mean that other optical modules, such as 10GBase-SR, are supported as well? Any clarification on how the transceivers interact with different optical modules would be greatly appreciated. Thanks in advance!
RX Mac segmented interface detailed information
I am using Ftile ethernet hard IP (400G configuration) . I complied the example test design with signal tap to monitor RX mac segmented interface and loaded on MA2700 . The kit is connected to a host with 400G capable NIC in it. I am using ping command and via wireshark I can see that host sends ARP request packet to the kit. As the ARP request packets are sent to the kit, I triggered STP and capture I have attached screenshot. you can see all data in the capture other than rx_mac data. rx mac data on clock -1 and 0 are as following -1 -> E39001000406000801000608AAEB6A17E390FFFFFFFFFFFFD5555555555555FB070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707 0 -> 070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707FDE831AB370000000000000000000000000000000000006501A8C0000000000000C801A8C0AAEB6A17 From wireshark I can see this ARP packet is 60bytes and all the fields matches with what I see in the o_rx_mac_data. Now I am trying to make sense of Rx mac segmented interface and I have following questions. rx mac inframe values are E000h and 000Fh meaning total 7 bits are 1 (logic high) indicating 56 byte packet but from payload is 60 bytes. So how do I equate for remining 4 bytes? in user guide o_rx_mac_eop_empty [47:0] signal is explained as "Indicates the number of empty bytes on the RX data signal, starting from the most significant byte (MSB). Valid only on EOP segments." I dont understand this statement completely so please help; as per signal tap waveform clock 0 is where packet ends and the value of bus is 4800h. I am not sure if and how this value can help equates for missing 4 bytes. Figure 44. Receiving Data Using the RX MAC Client Interface is little help- and small explanation below it (has typos i think) is not much help. Do you have more details and example for MAC segmented interface which you can share with me so that I can learn exact details on how to use this interface to receive incoming packets from Ftile. Using above signaltap screenshot and o_rx_mac_data values for clock -1 and 0; how do i detect sop? how do i use rx mac_sengemented interface to detect eop ? how do i use rx mac_sengemented interface detect exact length of ethernet frame which is being supplied during clock -1 and 0.Triple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis
Hi, I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the A5ED043AB32AE3V. The IP core issues an error during Analysis & Synthesis in Quartus Pro 2026.1. Error(18842): The ENABLE port on clock gate i_altera_pcs_pma_1g_hps|eth_tse_0|hps_gmii_adapter_instance|u_pcs_rx_clk_gated|altclkctrl_comp|altclkctrl_inst|clkena_inst is connected to a constant. It must be driven by a real signal. I checked the generated netlists. The error occurs in an encrypted section; thus I can not change anything. The usage of the IP core is straight forward. Connect to the Platform Designer project of the HPS, where I fed out EMAC0. There is nothing I can change during generation of the IP core nor its instantiation. For me this looks like (another) Agilex 5 bug. Regards Gerhard
F-tile ethernet hard ip in agilex7
I generate 200G ethernet F-tile hard ip that base on agilex7, the IP configuration as follow: Our current test setup uses our custom development boards interconnected with Mellanox CX-8. The link fails to come up regardless of whether the CX-8 is configured in forced mode or auto-negotiation mode. Could you advise on how I should troubleshoot this issue next? Additionally, I would like to ask: Does the F-Tile Ethernet Hard IP support filtering packets smaller than 64 bytes? I cannot find the corresponding configuration options in the IP configuration GUI.F-tile ethernet hard ip in agilex7
I generate 200G ethernet F-tile hard ip that base on agilex7, the IP configuration as follow: Our current test setup uses our custom development boards interconnected with Mellanox CX-8. The link fails to come up regardless of whether the CX-8 is configured in forced mode or auto-negotiation mode. Could you advise on how I should troubleshoot this issue next? Additionally, I would like to ask: Does the F-Tile Ethernet Hard IP support filtering packets smaller than 64 bytes? I cannot find the corresponding configuration options in the IP configuration GUI.
Agilex 7 F-Tile 200G hard IP de-feature clarification
There is a point in the Agilex 7 known issues list in UG-683584 for some silicon revisions The F-Tile Ethernet 200G Hard IP block is de-featured and cannot beused in production devices with OPNs that have no suffix (blank) or "B" suffix Does this mean that 200G "bonded" hard-IP is not supported in those older OPNs, such as 200GE-4 / 200GE-8 ? Or does it mean that all parts of 200G hard IP is de-featured? For example would FEC/PCS/MAC still work in 10/25/50GE-1 configurations?
