System console giving up when running the command "TEST_PHYSERIAL_LOOPBACK 0 1G 1000"
Hi, I have generated the design example for Low latency ethernet 10g mac intel fpga ip-- 10M/100M/1G/10G example design(Arria 10) by following the below document. https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10m-100m-1g-10g-ethernet-design-example.html While testing it on the hardware, I am getting the below error from system console. “error: master_write_32: This transaction did not complete in 60 seconds. System console is giving up. While executing “master_write_32 sport_id $address $wdata” (procedure “reg_write” line 7) invoked from within “reg_write $PHY_IP_BASE_ADDR $seq_control 0X111” (procedure “SETPHY_SPEED_1G” line 😎 invoked from within “CONFIG_IPORT $speed_test” (procedure “TEST_PHYSERIAL_LOOPBACK” line 10) invoked from within TEST_PHYSERIAL_LOOPBACK 0 1G 1000” I have changed the USB blaster frequency to 16MHz,6MHz but still I am getting the issue. Details: Quartus used : Quartus prime 22.2 Board :Intel arria 10 GX development board Device : 10AX115S2F45I1SG. Below are the clock pin assignments Name pin assigned mm_clk 125Mhz BD24 clk_125 ref_clk_1g 125MHz N37 REFCLK_SMA (modified using clk controller). ref_clk_10g 644.53125Mhz AA37 REFCLK_SFPethernet_100g_loopback_off
Hi, I have generated a low latency 100g design example by following the guide below: https://www.intel.com/content/www/us/en/docs/programmable/683371/16-1/quick-start-guide.html I tested the serial loopback on the development board, I was able to see the Rx and Tx stats. But when i wanted to disable the loopback , i made the loop_off in the .tcl scripts and tested on the development board but it was still showing Rx and Tx stats. Name of the board: ARRIA10 GX development board Device: 10AX115S2F45I1SG Below, I am sharing the .qar of the design and the system console window output when the loop_off is done in the tcl scripts.
TX sync header error insertion in Arria 10 GX
Hi, I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC. I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable. Packet Transmit and receive test is working good by viewing Rx stream port by Signal Tap. For error insertion test, I have set "Enable TX sync header error insertion" option in the parameter editor, and I drove the tx_err_ins PHY input port. But I have no Rx stream change after error insertion. In my thought, by receiving corrupted sync header in the RX, the rx_enh_blk_lock output port would go low. Do you have any method to confirm sync header error was inserted in the TX encoder? In another point, I have unclear description in the user guide: Table 24. 64b/66b Encoder and Decoder Parameters on Page 60, --- "Enable TX sync header error insertion" When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver. When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly. If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded. --- I can't find what "the error flag" is. Thank you for any help.
Agilex Triple Speed Ethernet tcl script error
Hi, I'm using AGFB014R24B2I3V device in my custom project. Generated hardware design by following TSE Onboard PHY chip reference design. To test SGMII interface for PHY 88E1512 using TSE IP, tcl script was executed, but getting error as attached snapshot. Is there anything I'm missing out here. Kindly help us to resolve this issue asap. -- Regards,
Got stuck during establishing ethernet Communicaton using Quartus prime and Nios software.
Dear Sir/Madam, I am currently working on establishing Ethernet communication between a Cyclone V FPGA (5CEFA7F27I7) and a DP83867IR Ethernet Physical Transceiver IC using Quartus Prime 16.0.0 and Nios II - Eclipse software. I have attached several files for reference, including screenshots of the schematic, QSYS configuration, and the .bdf file. Description: Configuration: QSYS Configuration: I am using a Nios II processor, Triple-speed Ethernet, and Scatter Gather DMA Controller IPs (one each for Tx and Rx). HDL File Generation: After generating the HDL (.sopcinfo) file from QSYS, I converted it into a .bsf file and included it as blocks in the .BDF file (Top Module). Additionally, I am using a self-created gmii_mii_mux block for mode selection and an eth_phy_reset block. Operating System: Micrium MicroC/OS-II is being used in nios ii software. Testing and Code: Initial Testing: I have verified the functionality of SDRAM and CFI_Flash, which are operating satisfactorily. Network Initialization: I created a thread to run the InitNetwork function. The main file (hello_world1.c) has been attached for your review. Manual Configuration: Since there are no existing libraries for the DP83867IR IC, I manually added the IC configuration and link_status_read functions in the Altera_Avalon_Tse.h and Altera_Avalon_Tse.c files. Current Issue: Detection and Configuration: The PHY is detected at address 0x00. However, it attempts to read the PHY ID from the remaining addresses, resulting in a warning: "Number of PHY connected is not equal to the number of channels; Number of PHY: 32, Channel: 1." Error Messages: The console indicates that the link is established and displays the user IP address. However, when attempting to ping the unit from a PC, the following errors occur: "Reply from 192.168.0.26: Destination host unreachable." "Request timed out." I would greatly appreciate your assistance in resolving these issues. Thank you for your support.
Need TSE reference Design
Hi, I've spent a lot of time searching on Google and within the Intel community, but I couldn't find the Arria II GX FPGA Reference Design for TSE using the GXB Transceiver. In my case, I'm using Quartus 18.1. The only reference design I found is AN633 for Arria II GX, but it seems to be problematic due to its outdated design for Quartus 9.1, and it's missing some IP components needed for Quartus 18.1. Could you please assist us by sharing the TSE reference design for Quartus 18.1 on the FPGA Arria II GX? Thank you.XL710 no connectivity with Brocade ICX 6610 switch
I'm having the following symptom: Host 1 has a Intel XL710 card installed. If I connect the host to a Brocade ICX6610-48P switch via a 1m QSFP+ DAC (tried both a QSFP+ and a QSFP28 DAC), ethtool shows RX crc errors and no connectivity is possible except DHCP, which somehow works. Monitoring the port via the switch shows packets going out and in. Monitoring the port on Host 1 shows only packets going out. If I connect Host 1 to Host 2 (Mellanox CX3), everything works. If I connect Host 2 to the switch, everything works. If I connect Host 1 to Host 2 and Host 2 to the switch, and bridge the two ports of the CX3, everything works. Another user reported similar results: https://serverfault.com/questions/1117009/cant-get-new-nic-working/1140838 I do not currently have the capability to scope QSFP+ traffic, so no idea what's actually going on on the wire.
Silicom Showcases FPGA SmartNIC Acceleration Cards for O-RAN Apps at MWC Barcelona 2022
Silicom specifically designed the Silicom FPGA SmartNIC N6011 as a 5G O-RAN platform using open Intel® technologies. It is custom designed to meet the real-time processing needs of 5G DUs and can be configured for a wide range of network deployments.
Agilex5 GTS Reset Sequence
I am looking to use the GTS reset sequencer to enable the GTS PMA/FEC Direct PHY. In the docs, there are these diagrams: For this, I have designed the following component (which I have also tried with ~system_reset): always @(posedge system_clk_100) begin if (system_reset) begin gts_i_tx_reset <= 1'b1; gts_i_rx_reset <= 1'b1; end else begin if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1) && (gts_o_tx_pll_locked==1'b0) && (gts_o_tx_ready==1'b0) && (gts_o_rx_ready==1'b0)) begin gts_i_tx_reset <= 1'b0; gts_i_rx_reset <= 1'b0; end end end However, it seems my board is still stuck in reset: Filename 'fpga/soc_system_base.rbf'. Load address: 0x90000000 Loading: ################################################################# ################################################################# ####### 2 MiB/s done Bytes transferred = 1998848 (1e8000 hex) .............................................................FPGA reconfiguration failed! Command 'load' failed: Error -110 FPGA not ready. Bridge reset aborted! And I believe it may be due to this. Does this design look ok? Or should I look elsewhere for the root of the issue? Thanks!
