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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Need TSE reference Design

Hi,

I've spent a lot of time searching on Google and within the Intel community, but I couldn't find the Arria II GX FPGA Reference Design for TSE using the GXB Transceiver. In my case, I'm using Quartus 18.1.

The only reference design I found is AN633 for Arria II GX, but it seems to be problematic due to its outdated design for Quartus 9.1, and it's missing some IP components needed for Quartus 18.1.

Could you please assist us by sharing the TSE reference design for Quartus 18.1 on the FPGA Arria II GX?

Thank you.

Ethernet

10 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    Thanks for submitting the issue. Allow me have some time to look into the issue and I will get back to you with findings.


    Best regards,

    zying


    • nome's avatar
      nome
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago
      Hi
      Thanks for your reply
      i I'll waiting your reply
      Thanks
      nome
  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi nome,


    May I know the OPN number and the quartus version 18.1 (standard or pro) ?


    Best regards,

    zying


    • nome's avatar
      nome
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hi ZiYing_Intel

      Thanks your Reply

      I am using Arria ii GX EP2AGX190FF35I3 obviously We are not using Pro version .

      I an using Quartus Prime Version 18.1.1 build 646 04/11/2019 SJ standard Edition.

      Thanks

      Nome

  • nome's avatar
    nome
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello

    Thanks for your Reply

    As you share pervious post TSE Reference Design for Arria 10 . I try in Quartus 18.1 design I am getting warning below

    Thanks

    Nome

  • nome's avatar
    nome
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi ZiYing_Intel,

    Thank you for your informative post.

    You mentioned the Arria 10 Reference Design, which includes IP for XCVR, PHY, and other components. However, it does not support IP in the Arria II GX FPGA.

    If you happen to have a reference design for the Arria II GX with GXB transceivers, could you please share it with us?

    Thanks,

    Nome

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi nome,


    Since the device that you are using is too old, we still can't found the tse example design that related to arria ll. I would suggest you to use a new device which now the tse example design that can support it. I am now close the case. If you have any issue after the case closed, please do feel free to submit another issue. There will have people reach out to you.


    Best regards,

    zying