Need TSE reference Design

Hi,

Thanks for submitting the issue. Allow me have some time to look into the issue and I will get back to you with findings.

Best regards,

zying

Hi nome,

May I know the OPN number and the quartus version 18.1 (standard or pro) ?

Best regards,

zying

Hi nome,

I can't find the exact opn triple speed ethernet example design for you but you may try refer link below as a reference https://www.intel.com/content/www/us/en/design-example/715131/arria-10-triple-speed-ethernet-and-native-phy-design-example.html

Best regards,

zying

Hello

Thanks for your Reply

As you share pervious post TSE Reference Design for Arria 10 . I try in Quartus 18.1 design I am getting warning below

Thanks

Nome

Hi Nome,

I send the .qar file here. Hope that this triple speed ethernet example design is useful to you.

Best regards,

zying

Hi ZiYing_Intel,

Thank you for your informative post.

You mentioned the Arria 10 Reference Design, which includes IP for XCVR, PHY, and other components. However, it does not support IP in the Arria II GX FPGA.

If you happen to have a reference design for the Arria II GX with GXB transceivers, could you please share it with us?

Thanks,

Nome

Hi nome,

I still can't find the triple speed ethernet example that related to Arria II since the device that you use is too old. However, you also can try find the design example through the link below https://www.rocketboards.org/foswiki/Main/WebHome

Best regards,

zying

Hi nome,

Since the device that you are using is too old, we still can't found the tse example design that related to arria ll. I would suggest you to use a new device which now the tse example design that can support it. I am now close the case. If you have any issue after the case closed, please do feel free to submit another issue. There will have people reach out to you.

Best regards,

zying