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Agilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation
Hi, I am using 2x25Gbit PCS/PMA function only (with FEC) and 2x10Gbit PCS/PMA function only (without FEC) in my Agilex 5 design (device A5ED043AB32AE3V, Quartus Pro 26.1). 25Gbit transceiver are using IO bank 4C while 10Gbit transceivers are using IO bank 1C There is one reference clock driving the GTS PLL as well as the PMA reference clock input of the Ethernet IP core for both the 25Gbit interface and the 10Gbit interface. They are located in the IO bank of their transceivers. There is one Reset Sequencer for 25Gbit and 10Gbit each. Quartus compiles the design without errors but the Design Assitant reports a Critical Error "IPC-40038 - Individual bit of Control Unit clock of Reset Sequencer IP can drive only a single instance of Ethernet or PCIE IP" Basically I followed the Use Case 1 chapter 5.6.1 of the GTS Transceiver PHY User Guide version 2026.03.13. Both PCS/PMA units of each type receive the same o_pma_cu_clk from their Reset Sequencer. In a Quad there is just one or two Ethernet Hard IPs but there are 4 PCS/PMA functions accordig to the same document. Can I safely ignore this Critical Warning, is the Warning wrong or do I miss something? Thank you Gerhard
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GerhardCadek
2 months ago Place IP & Transceiver
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Clarification on TX/RX P&N Invert feature support in TSE IP core
Hello, Based on the page below from the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs (version 25.1, “Analog Parameter Options” section), the “Enable TX P&N Invert” and “Enable RX P&N Invert” options are described as preliminary and not supported in hardware: 3.3.11. Analog Parameter Options However, according to the updated page for version 25.1.1, those same features are now marked as supported in hardware: 3.3.11. Analog Parameter Options In the Analog Parameters tab of the Triple-Speed Ethernet (TSE) Intel FPGA IP, these TX/RX P&N Invert options also appear as configurable parameters. Could you please confirm whether these features are expected to function in Quartus Prime Pro 25.1.1 and Quartus Prime Pro 25.3 when used in the TSE IP core? Also, could you please let us know what happens if we enable these P/N inversion options in Quartus 25.1, since the documentation indicates that they are not supported in hardware in that release? Thank you in advance for your help and clarification. Best regards,
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fa_fpga_enthusiast
11 months ago Place IP & Transceiver
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Boost IP-based Video Production Equipment Performance with Intel® FPGAs
Live video production presents many challenges including—but not limited to—interoperability, performance, latency, and connectivity. Intel® FPGAs can help you meet these challenges.
Evan_Pandya
4 years ago Place Blog
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RMA for EP4CGX110DF27I7N
Hi @[email protected], can you help us with the RMA for below case? Since we need to continue with the analysis to determine the root cause, the unit failed in field with our end customer. I’m attaching the FA from Flex. CPN: N0230475 Flex PN: CIE-N0230475 Intel PN: EP4CGX110DF27I7N Reference U91 Thank you for your collaboration in this matter. The I2C stage with FRU 1 on the motherboard involve U91 component and J15 connector, so continuity between signals I2C was checked but no issues where detected. The J15 and U91 component was checked on X-Ray but no solder issue was detected on component’s spheres. No passives components issues nor solder defects related to the stage. Due to the passive components, PCB issues and solder defects were discarded it means that the U91 component has an electrical damaged and I2C communication between FRU 1 and U91 is not working correctly. The U91 was send to replaced and the unit will be tested in order to completed its RMA process
PPere22
1 year ago Place IP & Transceiver
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5CGTFD5C5F23C7N
Hello, We are using 5CGTFD5C5F23C7N in our Product. While integrating peripherals, want to know VOL,VOH, IOL,IOH, VIL,VIH etc. Unable to get it from datasheet. Please share the details. Thanks.
YRP
1 year ago Place IP & Transceiver
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Ask about the difference between "EPF10K30RI208-4N" and "EPF10K30RI208-4"
Ask about the difference between "EPF10K30RI208-4N" and "EPF10K30RI208-4" Thanks in advance. James
James-
2 years ago Place IP & Transceiver
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need a high-temperature FPGA chip which can work in the150 degree environment
Our product needs to work in the150 degree environment. In the early stage of the project, chip selection requires a high-temperature FPGA product series with a main frequency of 40MHz or above
Yuexia
2 years ago Place IP & Transceiver
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