Agilex5 GTS Reset Sequence

Hi @CheePin_C_Intel!

Thanks for your response I will try to answer:

1: The following is my qsys design:

...
// GTS signals
wire gts_i_rx_cdr_refclk;
wire gts_i_tx_pll_refclk;
reg gts_i_tx_reset, gts_i_rx_reset;
wire gts_o_tx_reset_ack, gts_o_rx_reset_ack;
wire gts_i_tx_coreclkin, gts_i_rx_coreclkin;
wire gts_o_tx_clkout, gts_o_rx_clkout;
wire gts_o_tx_serial_data, gts_o_tx_serial_data_n;
wire gts_i_rx_serial_data, gts_i_rx_serial_data_n;
wire [79:0] gts_i_tx_parallel_data;
wire [79:0] gts_o_rx_parallel_data;
wire osc_clk;
wire osc_rst;
wire [31:0] osc_pattern_o;
wire raw2s_clk;
wire raw2s_rst;
wire [31:0] raw2s_data_i;

assign gts_i_tx_coreclkin = gts_o_tx_clkout;
assign gts_i_rx_coreclkin = gts_o_rx_clkout;
//assign gts_i_tx_parallel_data[38] = 1'b0; // TX PMA Interface Data Valid
assign gts_i_tx_parallel_data[31:0] = osc_pattern_o;
assign raw2s_data_i = gts_o_rx_parallel_data[31:0];
assign gts_i_rx_serial_data = gts_o_tx_serial_data;
assign gts_i_rx_serial_data_n = gts_o_tx_serial_data_n;

always @(posedge system_clk_100) begin
      if (system_reset) begin
            gts_i_tx_reset <= 1'b1;
            gts_i_rx_reset <= 1'b1;
      end else begin
            if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1)) begin
                  gts_i_tx_reset <= 1'b0;
                  gts_i_rx_reset <= 1'b0;
            end
      end
end

//// Oscillator
assign osc_clk = gts_o_tx_clkout;
assign osc_rst = system_reset;


// Qsys Top module
qsys_top soc_inst (
...
.intel_directphy_gts_1_i_rx_cdr_refclk_p_clk                     (REFCLK),
.intel_directphy_gts_1_i_tx_pll_refclk_p_clk                     (REFCLK),
.intel_directphy_gts_1_i_tx_reset_tx_reset                       (gts_i_tx_reset),
.intel_directphy_gts_1_i_rx_reset_rx_reset                       (gts_i_rx_reset),
.intel_directphy_gts_1_o_tx_reset_ack_tx_reset_ack               (gts_o_tx_reset_ack),
.intel_directphy_gts_1_o_rx_reset_ack_rx_reset_ack               (gts_o_rx_reset_ack),
.intel_directphy_gts_1_i_tx_coreclkin_clk                        (gts_i_tx_coreclkin),
.intel_directphy_gts_1_i_rx_coreclkin_clk                        (gts_i_rx_coreclkin),
.intel_directphy_gts_1_o_tx_clkout_clk                           (gts_o_tx_clkout),
.intel_directphy_gts_1_o_rx_clkout_clk                           (gts_o_rx_clkout),
.intel_directphy_gts_1_o_tx_serial_data_o_tx_serial_data         (gts_o_tx_serial_data),
.intel_directphy_gts_1_o_tx_serial_data_n_o_tx_serial_data_n     (gts_o_tx_serial_data_n),
.intel_directphy_gts_1_i_rx_serial_data_i_rx_serial_data         (gts_i_rx_serial_data),
.intel_directphy_gts_1_i_rx_serial_data_n_i_rx_serial_data_n     (gts_i_rx_serial_data_n),
.intel_directphy_gts_1_i_tx_parallel_data_i_tx_parallel_data     (gts_i_tx_parallel_data),
.intel_directphy_gts_1_o_rx_parallel_data_o_rx_parallel_data     (gts_o_rx_parallel_data),
.intel_srcss_gts_1_i_src_rs_priority_src_rs_priority             (1'b1),
.oscillator_0_clk_clk                                            (osc_clk),
.oscillator_0_rst_reset                                          (osc_rst),
.oscillator_0_oscillator_pattern_o_new_signal                    (osc_pattern_o),
.raw_to_stream_1_raw_data_in_i_new_signal                        (raw2s_data_i),
...
);
...

I then generate the HDL, and compile the bitstream - and load over TFTP.

2: Using this devkit

3: This is not an example design generated from Quartus - I am having trouble there too (different thread for that topic)

Thanks! This is reflected now in the recent post

Hi in fact the same issue is occurring with the JTAG boot