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Re: I want to use a lot of 10GBase-R PHY on an Agilex 5 E
Hi, Based on the screenshot alone, I don’t see any obvious anomalies. That said, it’s difficult to determine whether the configuration fully aligns with your specific use case from the screenshot alone. I would recommend cross‑checking the configuration against your target requirements and running a functional simulation to verify that it behaves as expected for your intended application. Please let me know if you have any concerns. Thank you.6Views0likes0CommentsRe: JESD240B - No license
Hi, Based on the screenshot you shared, it appears that the JESD204B IP license may not be detected in your Quartus environment. Could you please help confirm whether the JESD204B‑specific IP license has been obtained after purchase and added to your Quartus license file? If the license has not yet been set up, please let me know and I’d be happy to engage our licensing expert to assist you with enabling the license. Feel free to reach out if you have any questions or need further assistance. Thank you.11Views0likes1CommentRe: Technical Inquiry regarding DPCU Block for CPRI IP Single-Trip Delay Calibration
Hi, I’d like to share an update based on a response from the factory team. They have confirmed that the DPCU block is packaged within the CPRI IP, and it can be instantiated directly at the top level using the pll_dpcu module. This can then be connected to the IO PLL as needed. Below is an example of how the instantiation would look: pll_dpcu #( // parameters ) pll_dpcu_inst ( .clk (clk), .reset_n (rst_n) // ... ); I’ve tested this instantiation on my side and confirmed that the module appears correctly after Analysis & Synthesis in Quartus completes. Please try this approach and let me know how it goes, or if you have any questions or issues along the way. Thank you.0Views0likes1CommentRe: Technical Inquiry regarding DPCU Block for CPRI IP Single-Trip Delay Calibration
Hi, Just to keep you posted that I am still pending for Factory's valid response on this. I will continue to follow up with them and update you again on the progress by end of the week or as soon as there is any valid response. Please ping me if you do not hear back from me. Sorry for the delay. Thank you.9Views0likes0CommentsRe: Agilex 5: Cascading DSPs in tensor-mode doesn't work
Hi, As I understand, you have questions regarding the Agilex DSP behavior, where the observed output does not match your expectations. To ensure we are aligned and to help me better understand the issue, could you please assist with the following: Simulation case Please share a simple test design and simulation setup, with steps to replicate the simulation, along with a brief description or illustration of the expected behavior. Hardware reproduction Please also share a minimal hardware test design that can reproduce the issue, together with steps to replicate and SignalTap captures highlighting the unexpected behavior. This information will help me better understand the DSP IP configuration, test setup, and observed behavior, and will greatly facilitate further debugging. Please feel free to let me know if you have any questions or need clarification. Thank you.18Views0likes0Comments