CheepinC_altera
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Re: Agilex 7 slew rate reconfiguration
Hi, Thanks for your clarification that you are referring to F-tile. As per my previous note, there is no configurable parameters related to TX slew‑rate control. Could you confirm whether you are instead referring to other PMA analog settings, such as TX pre‑emphasis? Thank you.2Views0likes1CommentRe: Floating point operation on Cyclone 10 GX
Hi Frank, Thank you for the update. I’m glad to hear that the Native Floating‑Point DSP IP has resolved the rounding issue. From my understanding, the Native DSP IP allows users to access the DSP block directly, without relying on inference. Please let me know if you have any questions or concerns. Thank you.4Views0likes0CommentsRe: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
Hi, After consulting with our DisplayPort (DP) IP experts, it appears that our DP is currently not operating in bonded mode for multi‑lane support. You may want to explore our DP IP. Please let me know if you have any questions or concerns. Thank you.5Views0likes0CommentsRe: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
Hi, Thank you for your question. From your description, you are asking about the maximum data rate supported by the Stratix 10 ATX PLL when operating in bonded mode. You are correct — according to AN 778: Intel® Stratix® 10 L‑Tile/H‑Tile Transceiver Usage, channel bonding is not supported for data rates above 17.4 Gbps. We understand this may be inconvenient, and we appreciate your patience. In parallel, I am consulting with our DisplayPort IP experts to confirm whether the DP IP can support 20 Gbps while using bonded channels. I will update you as soon as I receive a definitive response. If you do not hear back from me by the end of next week, please feel free to ping me. Thank you.1View0likes0CommentsRe: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
Hi, Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.4Views0likes0CommentsRe: Floating point operation on Cyclone 10 GX
Hi, Thank you for your question. Based on your inquiry regarding the C10GX floating‑point DSP IP and its rounding behavior, I reviewed the available C10GX documentation. I was not able to find any reference indicating support for fused multiply‑add (FMA) operations, which suggests that FMA may not be implemented in this IP. As a next step, could you try performing the same test using the Native Floating-Point DSP IP to see if there is any different in the observation. If you have additional questions or need further clarification, please feel free to let me know. Thank you.13Views0likes2CommentsRe: Agilex 7 slew rate reconfiguration
Hi, From your inquiry, I understand that you are looking into reconfiguring the TX slew rate for the Agilex 7 XCVR. Please correct me if my assumption is incorrect, but I am presuming you are referring to the F‑tile transceiver. For your information, after reviewing the F‑Tile Architecture and PMA and FEC Direct PHY IP User Guide, I was not able to locate any specific info or configurable parameters related to TX slew‑rate control. Could you confirm whether you are instead referring to other PMA analog settings, such as TX pre‑emphasis? Please let me know if you have any concerns or if you can share more context about your requirement. Thank you.10Views0likes2Comments