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Re: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Hi Brian, Thank you for the update. I’m glad to hear that you’ve successfully fit the bank with PCIe x2, three duplex channels, and one TX-only channel. Regarding your latest question on using PCIe x4 + two custom PHYs, could you please confirm whether the custom PHYs are full duplex? If they are, based on Figure 4‑5: 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x2 and x4 Channel Placement in the Cyclone V Device Handbook, Volume 2: Transceivers, CH0–CH3 would be occupied by PCIe x4, with the CMU PLL sourced from CH4. In this configuration, there would not be sufficient resources to accommodate two additional full-duplex custom PHYs. Regarding the reconfiguration controller, apologies for the earlier confusion, and thank you for pointing it out. To clarify, in Cyclone V devices, a maximum of one reconfiguration controller is allowed per transceiver bank (three transceiver channels). Please let me know if you have any questions. Thank you.7Views0likes1CommentRe: FIR IP configured for Interpolation
Hi, As I tried to replicate your simulation, I noticed that I would need a few other settings of your FIR II IP ie Coefficient Settings, Coefficients, Input/Output Options, Implementation Options and Reconfigurability. You may share with me the IP megawizard files. Thank you.47Views0likes0CommentsRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Hi Brian, For your information, I have created a test design with the following configuration, and it successfully passes Fitter compilation: One fPLL driving duplex channels (CH3, CH5) and TX (CH4) One fPLL driving duplex channel (CH2) One CMU (CH4) driving PCIe PIPE PHY x2 (CH0, CH1) A single reconfiguration controller connected to all channels From my observation, only one reconfiguration controller can be instantiated in the design. This is likely due to the fact that there is only one calibration block in the CV device. This would also explain your earlier observation—when more than one reconfiguration controller is included, it results in compilation issues. Please let me know if you have any questions or concerns. Thank you.7Views0likes3CommentsRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Hi Brian, Just to update you that I am still running tests using Native PHY designs to check the placement rules. Could you please share the test design that reproduces the reconfiguration placement issue? I would like to replicate the issue on my side and continue debugging from there. Regarding your question on “why the PCIe IP requires CH4 instead of CH1 in the first place”: If I understand you correctly, you are asking why, in PCIe x2 mode, CH4 RX is required as the CMU PLL. If so, for clarification, the CMU PLLs in CH1 and CH4 also function as the CDRs. When PCIe x2 uses CH0 and CH1, there is no additional CMU PLL available in CH1. As a result, the design must use the CMU PLL in CH4. Please let me know if I misunderstood your question or if you need any further clarification. Thank you.5Views0likes2CommentsRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Hi Brian, Thanks for your update. Please allow me some time to look into this observation "quick placement test it never work unless [CH3 CH5] only". I will provide you an update on the progress by end of this week or as soon as there is any valid finding.10Views0likes4CommentsRe: FIR IP configured for Interpolation
saasha Would you mind to help to create a simple testbench design in QuestaSim that reproduces the issue you’re observing? Having a minimal simulation case would greatly help with replication and debugging on our side. It would also be helpful if you could share the step-by-step procedure to run the simulation. Additionally, please let us know the specific device you are using. Thank you for your support.13Views0likes0CommentsRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Hi, Thank you for the update. Based on my understanding, you are planning to implement the following configuration: PCIe x2 + 1 CMU (CH4) CH2 with fPLL0 CH3, CH4 (TX‑only), and CH5 with fPLL1 From a theoretical standpoint, this configuration appears feasible. I would recommend creating a small test design and running it through the Fitter to verify compliance with any internal placement rules. Please let me know if you have any questions or if there are any concerns. Thank you.9Views0likes9CommentsRe: Agilex5: How to use a GTS refclk to clock the FPGA fabric?
FvM Appreciate your help on this case. Your explanation and elaboration are very helpful. zener Feel free to test out Frank's later recommendation which is compiling correctly and keep us posted if there is any inquiry. Thank you.11Views0likes0Comments