CheepinC_altera
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Re: Where is High Speed Transceiver Demo Design in FPGA Wiki ?
Hi TSUGI, Sorry for the delay. Seems like there is a glitch with the system recently which is causing issue for me to add new post. For your information, I managed to locate a few S10 Superlite IV design links after consulting the admin. Would you mind to check if you are able to download them using the following links? Please let me know if there is any concern. Thank you. 6. Superlite IV (using Native PHY) (with FEC) PAM4 Updated (27/04/2021) Stratix 10 TX SI Board (Prod) : 1.8Tb Superlite IV Demo design using 18 times 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (+ I2C) (Native PHY + KPFEC) S10TX-SIBoard-SuperliteIV-Etile-18x-2-lanes-53Gbps-Native-Phy-Prod.zip (20.4 B72) (12/02/2019) Stratix 10 TX SI Board (S1) : 100G Superlite IV Demo design using 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 100 Gbps of raw data (Native PHY + KPFEC) s10tx-siboard-superliteiv-etile-2x2-lanes-53gbps-native-phy-dual-qsfp.zip (18.1.1 B263) (17/04/2019) Stratix 10 TX SI Board (S1) : 400G Superlite IV Demo design using 8 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 400 Gbps of raw data (+ I2C & Fan Control + tested with 400G Optics) (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_1x8_lanes_53Gbps_Native_Phy.zip (18.1.2 B277) (13/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_1x12_lanes_53Gbps_Native_Phy.zip (18.1.1 B263) (08/03/2019) Stratix 10 TX SI Board (S1) : 1.8Tb Superlite IV Demo design using 3 times 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_3x12_lanes_53Gbps_Native_Phy.zip (18.1.2 B277) NRZ (19/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 24 lanes at 25.78125 Gbps with NRZ encoding and RS-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_1x_24_lanes_26Gbps_Native_Phy.zip (18.1.1 B263)0Views0likes0CommentsRe: Enabling DFE Adaptation on Cyclone 10 GX
Hi, Sorry for delay. There seems to be some glitches in the system which causes some issues for me to add post. Thank you for reaching out. Based on my understanding on the current observation, the Transceiver Toolkit seems to be accessing internal DFE registers, which are not formally exposed for user access. Since DFE adaptation is not officially supported, I’m unable to enable this feature. If you would like to explore this further, I recommend engaging your local sales representative, who can work with our factory team on your request. Please note that this process typically requires sufficient business justification. Regarding your PMA analog tuning in Toolkit, just to check, if you perform auto-sweep with the equalization features (apart from DFE), does it help to find an optimal settings with low BER? Feel free to let me know if you have any questions or need additional clarification. Thank you for your understanding.0Views0likes0CommentsRe: Enabling DFE Adaptation on Cyclone 10 GX
Hi, Sorry for the delay. As I searched through the Cyclone 10 XCVR user guide, seems like I am unable to locate any specific info on the support of the DFE adaptation in C10 GX devices. As I checked with the C10 GX Native PHY, seems like there is no specific DFE adaptation feature as well. For your information, I have also come across one of the previous community post which seems to explain that there is no official DFE adaptation support in C10 GX devices at (https://community.altera.com/discussions/fpga-device/how-can-i-set-the-dfe-decision-feedback-equalization-in-adaptive-mode-for-the-10/204374) Based on these, it seems like there is no official support of DFE adaptation in C10GX XCVR. Sorry for the inconvenience.10Views0likes0CommentsRe: Transceiver data corruption
Hi, One possible cause of intermittent bit errors could be related to signal integrity issues. Have you had a chance to enable serial loopback and check if the issue persists? This step can help isolate whether the problem is due to signal integrity or something else.2Views0likes0CommentsRe: Transceiver data corruption
Hi, Thank you for your question regarding implementing a simple test design with the Agilex 5 GTS transceiver. To help you get started quickly, I recommend referring to the IP-generated example design described in the GTS Transceiver PHY User Guide under the section “GTS PMA/FEC Direct PHY IP Example Design.” You can select an example design that is closest to your target configuration, verify its functionality, and then proceed with customizing it to meet your specific requirements. Generally the example designs support simulation and hardware. Please let me know if you have any further questions or need additional clarification. Thank you.11Views1like2CommentsRe: JESD204B Multi-Link configuration with Different Link Parameters on Stratix10
Hi, For a quick and straightforward start, I recommend creating three separate single-link instances first, and then integrating them into a single project. This approach should help simplify the initial setup and reduce potential integration issues. Please let me know if you have any questions or need further assistance.4Views0likes0Comments