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CheepinC_altera
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Re: currently evaluating FPGA solutions
Hi Sudip, Thanks for your update. For your information, I have notified our Sales & Field team in India to get in touch with you. Regarding your latest inquiries, let me address each point directly based on the available technical documentation: 1. Native JESD204B IP for Arria 10 (including SoC variants) Yes, we support in-house JESD204B IP in Arria 10. The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) devices AN 810: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report , and Altera provides a design example of the JESD204B Intel FPGA IP targeting Arria 10 devices. JESD204B Arria 10 FPGA IP Design Example User GuideThe JESD204B IP is a high-speed point-to-point serial interface for DAC or ADC converters to transfer data to FPGA devices, running at a maximum data rate of 17.4 Gbps. About the JESD204B IP This is Altera's own native IP — not a third-party solution. 2. Quartus Prime Version and Arria 10 Variants The JESD204B IP is still supported in the latest Quartus Pro version. 3. Licensing The IP support evaluation mode which allows you to evaluate the IP core in simulation and hardware, before deciding to purchase a full production IP core license. The ordering code for the JESD204B IP is IPS-JESD204. Release Information 4. Reference Design for ADRV9029 on Arria 10 SoC There seems to be a documented reference design which should be applicable to your scenario. You may refer to the AN 934: Using Flexible Radio Platform with Arria 10 FPGA and ADI ADRV9029 Sub6G EBZ Board for further details. Please let me know if there is any inquiry. Thank you.1View0likes0CommentsRe: Request for Technical Meeting – FPGA Selection, ADRV9029 Integration, and Procurement Support
Hi, I believe this is a similar post with another thread - currently evaluating FPGA solutions. I have posted some notes in the other thread. Let's set this thread to close and continue to follow up in the other thread. Thank you.13Views0likes0CommentsRe: currently evaluating FPGA solutions
Hi, As I understand it, you are evaluating the suitable FPGA for your JESD204C application. Can I check with you if you are aware of your local Altera Sales/Field team? If not, feel free to let me know your region and I will reach out to our Sales/Field team to get in touch with you on the suitable FPGA solution for your project. For your information, the Arria 10 does not support in-house JESD204C IP. Instead, it is supported through third party IP. For example: A third-party JESD204C Transmitter and Receiver IP from Logic Fruit Global Technologies is available in Production status, supporting Arria 10 SX FPGA, Arria 10 GT FPGA, and Arria V GZ FPGA. JESD204C TRANSMITTER AND RECEIVER IP This IP offers better DC balance, clock recovery, and data alignment compared to JESD204B. JESD204C TRANSMITTER AND RECEIVER IP The bit overhead is 3.125%, which is much smaller than JESD204B (~25%). JESD204C TRANSMITTER AND RECEIVER IP Note this is a partner IP, not Altera's own first-party JESD204C core. Please let me know if there is any inquiry. Thank you.13Views0likes2CommentsRe: How to manual control the E-Tile transceiver's CDR mode of agilex 7
Hi, I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much.2Views0likes0CommentsRe: Serial Lite IV - Rx Simulation Issues
Hi host, I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much.0Views0likes0CommentsRe: Three 9x9 multipliers in one DSP
Hi, Sorry for the delay in responding. I overlooked this inquiry. As I understand it, you would like to pack three 9×9 multipliers into a single DSP block. Currently, your compilation is mapping each 9×9 multiplier to a separate DSP block. For your information, when sufficient DSP resources are available, Quartus typically assigns one DSP block per multiplier to optimize performance and simplify implementation. Packing multiple multipliers into a single DSP block is generally considered only when DSP resources are constrained. Similar to the forum post you referenced, you may try increasing the overall DSP utilization or applying a Logic Lock region to encourage resource packing. These approaches may help Quartus select a more resource-efficient implementation. Please let me know if you have any further questions or if you would like to share your design details for further review. Thank you.2Views0likes2CommentsRe: Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Hi Himanshu, I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much.10Views0likes0CommentsRe: Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Hi Himanshu, Thank you for following up. I checked our internal database and found that the fgt_rx_signal_detect_lfps_port was originally intended for USB-related applications. However, the Direct PHY IP does not support USB mode. As a result, this port was removed from the Direct PHY IP implementation and is not exposed to users. At present, there is no supported method to enable or access this port in the latest Quartus release. Sorry for any inconvenience this may cause.16Views0likes1Comment