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CheepinC_altera
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Re: Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Hi, Regarding the 2D eye diagram inquiry, for your information, the Agilex 7 F-Tile Transceiver Toolkit does not support a 2D eye plot. It provides scalar measurements ie eye heights and widths. You might need to use oscilloscope for 2D eye diagram measurement as a workaround. Sorry for the inconvenience.1View0likes0CommentsRe: Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Hi, As I understand it, you have several inquiries related to BER performance on the F-Tile Transceiver. Let me address them one by one. Regarding your observation that the external loopback shows a non-zero BER while the internal loopback reports zero BER, this is expected behavior. In internal loopback mode, the transmitted data is looped back to the receiver within the transceiver itself, bypassing the external channel. As a result, the signal is not exposed to any external signal integrity impairments such as channel loss, noise, crosstalk, or reflections. In contrast, external loopback exercises the complete signal path, including the PCB traces, connectors, cables, and other channel components. Therefore, any signal integrity degradation along the external path may contribute to bit errors and result in a non-zero BER. By the way, I was unable to locate the test design and Transceiver Toolkit results that you referenced. It is possible that I may have missed them. Could you please point me to the relevant files or share them again for review? Please let me know if you have any concerns or additional questions. Thank you.0Views0likes0CommentsRe: Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Hi amol, Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.1View0likes0CommentsRe: GTS Reset Sequencer IP o_refclk_on_ack
Hi, For your information, I checked the GTS Transceiver PHY User Guide for a minimum pulse width specification on o_refclk_on_ack . Unfortunately, I could not find any documented minimum pulse width requirement for this signal in the available documentation. As a result, I am unable to confirm whether a 100 MHz sampling clock (10 ns period) can reliably capture the pulse under all conditions. Given this uncertainty, I would recommend the following approaches: Use edge detection as a robust design practice Instead of directly sampling o_refclk_on_ack with the system clock, consider implementing an edge-detection circuit and synchronizing the detected event into your clock domain. This helps avoid missing a narrow pulse. Verify the pulse width through simulation Run functional or timing simulations to observe the expected pulse width of o_refclk_on_ack and determine whether it can be consistently captured by a 100 MHz clock. Measure the signal in hardware using Signal Tap Capture o_refclk_on_ack with Signal Tap to verify its pulse width and behavior in the actual device implementation. I hope this helps. Please let me know if you have any further questions or need additional assistance. Thank you.4Views0likes2CommentsRe: Agilex-5 supported Transceivers
Hi, Thank you for the update. To facilitate further debugging, I recommend using the XCVR Toolkit, or alternatively a simple XCVR design with SignalTap, to monitor the transceiver status. The XCVR Toolkit would be the quickest approach to get started. Please follow these steps: Generate an example design using the GTS PMA/FEC Direct PHY IP and target the relevant development kit. Select a simple configuration from the available example design options, preferably using a single channel and a lower data rate. Enable the XCVR Toolkit by following the instructions in the GTS Transceiver PHY User Guide, under the “GTS Transceiver Debugging Flow Walkthrough” section. Assign the transceiver pins to the SFP+ interface. Compile the design and program the resulting SOF file onto the development kit. In the XCVR Toolkit, enable internal serial loopback and monitor the TX and RX lock/status indicators. Run the PRBS test with internal serial loopback enabled. This will help verify the basic transceiver functionality without depending on signal integrity or an external loopback connection. Disable internal serial loopback, plug in the SFP+ module, and repeat the test. Please share the observations from both tests, including the TX/RX lock status, PRBS test results, and any reported errors. Please let me know if you have any questions.5Views0likes0Comments