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Re: Where is High Speed Transceiver Demo Design in FPGA Wiki ?
Hi, Sorry for the delay. The following are the archive for Agilex F-Tile designs that I could locate. Can you help to check out. Thank you. 1. Multi-Prbs Generators and Checkers (28/04/2021) Collection of Multi-Prbs Generators and Verifiers used in various transceiver demo's with different bit widths: 32-bit, 64-bit, 128-bit, and 256-bit. Includes test bench as well. multi-prbs-generators-checkers.zip 2. Supporting documentation for the F-tile Demo Designs Soft PRBS Demo designs (with/without RSFEC) agilex-f-tile-demo-designs.pdf Updated (03/02/2022) Superlite II designs agilex-f-tile-superlite-ii-demo-designs.pdf Updated (09/02/2022) Superlite IV designs agilex-f-tile-superlite-iv-demo-designs.pdf Updated (18/02/2022) 3. Description of all F-tile Demo Designs (Excel file) Updated (15/02/2022) description-of-designs.xlsx (V1.6) 4. Library of C-functions for F-tile transceivers using AVMM Interfaces Updated (28/01/2022) Complete library of C-functions/drivers for F-tile f-tile-software.zip (V1.9) 5. Script with useful procedures for use in the system console with Agilex F-tile New (12/08/2022) Functions to be used with F-tile PHY-Direct/FEC-Direct designs/F-tile Ethernet Hard IP designs (controlling loopbacks, showing PMA settings, performing EHM, setting Media mode to VSR/Optics etc.). Requires NDME to be enabled. Supports both FGT and FHT. ttk-helper-ftile.tcl (V1.0) 6. Soft PRBS with RSFEC Demo Designs Intel Agilex® device I-Series PCIe development kit NEW (04/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 2x200G Aggregate mode using FGT transceivers connected to QSFPDD1 agilex-pcie-devkit-prbs-1x8ch-kpfec-ftile-2x200gbps-aggr.zip (21.4 B67) NEW (11/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4 channel 25.78125 Gbps soft PRBS test design with RSFEC (528,514) in 2x100G Aggregate mode using FGT transceivers connected to QSFPDD0 and QSFPDD1 agilex-pcie-devkit-prbs-2x4ch-rsfec-ftile-100gbps-aggr.zip (21.3 B170) Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD1 agilex-pcie-devkit-prbs-1x8ch-kpfec-ftile-400gbps-aggr.zip (21.4 B67) NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 200G Aggregate mode using FGT transceivers connected to QSFPDD's agilex-pcie-devkit-prbs-2x4ch-kpfec-ftile-200gbps-aggr.zip (21.3 B170) Updated (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to QSFPDD's + dynamically reconfigurable internal noise. agilex-pcie-devkit-prbs-2x4x1ch-rsfec-ftile-53gbps-fract-int-noise.zip (21.4 B67) NEW (11/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 3x4x1 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to QSFPDD's agilex-pcie-devkit-prbs-3x4x1ch-rsfec-ftile-53gbps-fract.zip (21.4 B67) (13/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel NRZ 25.7815 Gbps soft PRBS test design with RSFEC (528,514) Fractured mode using FGT transceivers connected to QSFPDD's agilex-pcie-devkit-prbs-2x4x1ch-rsfec-ftile-26gbps-fract.zip (21.3 B170) Intel Agilex® device I-Series SI/SOC Board NEW (06/12/2021) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): 2x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0 and QSFPDD1 agilex-si-board-prbs-2x8ch-kpfec-ftile-400gbps-aggr.zip (21.3 B170) NEW (06/12/2021) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile device): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0 agilex-si-board-prbs-1x8ch-kpfec-ftile-400gbps-aggr.zip (21.3 B170) Intel Agilex® device I-Series HS Demo Board (17/09/2021) Intel Agilex® device I-Series HS Demo Board (ES Version): 2x4 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to FMC+ agilex-hs-demo-prbs-2x4ch-rsfec-ftile-53gbps-fract-fmc.zip (21.2 B72) Updated (28/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 106 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FHT transceivers connected to OSFP800 agilex-hs-demo-prbs-4x1ch-kpfec-ftile-106gbps-fract-fht.zip (21.4 B67) NEW (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel NRZ 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FHT transceivers connected to OSFP800 agilex-hs-demo-prbs-4x1ch-kpfec-ftile-53gbps-nrz-fract-fht.zip (21.4 B67) 7. Soft PRBS Demo Designs (no FEC) Intel Agilex® device I-Series SI/SOC Board NEW (02/02/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): 2x8x1 channel 53Gbps PAM4 soft PRBS test design using FGT transceivers connected to QSFPDD0 and QSFPDD1 agilex-si-board-prbs-2x8x1ch-ftile-53gbps.zip (21.4 B67) Intel Agilex® device I-Series PCIe development kit Updated (31/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's with dynamically reconfigurable internal noise logic. agilex-pcie-devkit-prbs-2x4x1ch-ftile-53gbps-int-noise (21.4 B67) (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel NRZ 25.78125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's agilex-pcie-devkit-prbs-2x4x1ch-ftile-26gbps.zip (21.3 B170) (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's agilex-pcie-devkit-prbs-2x4x1ch-ftile-53gbps.zip (21.3 B170) (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 3x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's agilex-pcie-devkit-prbs-3x4x1ch-ftile-53gbps.zip (21.3 B170) Intel Agilex® device I-Series HS Demo Board (20/09/2021) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x4 channel NRZ 25.78125 Gbps soft PRBS test design using FGT transceivers connected to FMC+ agilex-hs-demo-prbs-4x4ch-ftile-26gbps-fmc.zip (21.2 B72) Updated (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 53.125 Gbps soft PRBS test design using FHT transceivers connected to OSFP800 agilex-hs-demo-prbs-4x1ch-ftile-53gbps-fht.zip (21.4 B67) NEW (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel NRZ 53.125 Gbps soft PRBS test design using FHT transceivers connected to OSFP800 agilex-hs-demo-prbs-4x1ch-ftile-53gbps-nrz-fht.zip (21.4 B67) Updated (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 106 Gbps soft PRBS test design using FHT transceivers connected to OSFP800 agilex-hs-demo-prbs-4x1ch-ftile-106gbps-fht.zip (21.4 B67) 8. Superlite II V4 (with/without KR FEC) New (10/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 design using 2 times 4 lanes at 25.78125 Gbps to transport 100 Gbps of raw data. agilex-pcie-devkit-superliteii-v4-ftile-fgt-2x4-lanes-26gbps.zip (21.4 B67) NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 with soft KR-FEC Demo design using 2 times 4 lanes at 10.3125 Gbps to transport 40 Gbps of raw data agilex-pcie-devkit-superliteii-v4-soft-krfec-ftile-fgt-2x4-lanes.zip (21.4, can be programmed using 21.3) Updated (10/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 design using 2 times 4 lanes at 10.3125 Gbps to transport 40 Gbps of raw data. agilex-pcie-devkit-superliteii-v4-ftile-fgt-2x4-lanes-10gbps.zip (21.4 B67) 9. Superlite IV (RSFEC) Intel Agilex® device I-Series SI/SOC Board NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus), total bandwidth = 4x400Gbps = 1.6 Tbps agilex-si-board-superliteiv-ftile-fgt-2x200g-4x8-lanes.zip (21.4 B67) NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus), total bandwidth = 4x600Gbps = 2.4 Tbps agilex-si-board-superliteiv-ftile-fgt-3x200g-4x12-lanes (21.4 B67) Intel Agilex® device I-Series PCIe development kit NEW (26/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 4 instances of 1 PHY direct IP configured in 100Gbps with KPFEC, bonded across 2 lanes at 53.125 Gbps to transport 100 Gbps of raw data (transparent transmission of a 256-bit bus), total bandwidth = 4x100Gbps = 400 Gbps. agilex-pcie-devkit-superliteiv-ftile-fgt-1x100g-4x2-lanes.zip (21.4 B67) NEW (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus) agilex-pcie-devkit-superliteiv-ftile-fgt-3x200g-1x12-lanes.zip (21.4 B67) Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus) agilex-pcie-devkit-superliteiv-ftile-fgt-2x200g-1x8-lanes.zip (21.4 B67) 10. 400GbE (8/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 400GbE (400G-8) Example Demo design using QSFPDD1 agilex-pcie-devkit-400gbe-8-fgt-example-design.zip (21.3 B170) (8/10/2021) Intel Agilex® device I-Series HS Demo Board (ES Version): 400GbE (400G-4) Demo design using OSFP800 agilex-hs-demo-400gbe-4-fht-example-design.zip (21.3 B170) 11. 100GbE NEW (30/11/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 100GbE (100G-4) with RSFEC(528,514) 4x25.78125 Gbps Example Demo design using QSFPDD1 agilex-pcie-devkit-100gbe-4-fgt-example-design.zip (21.3 B170) 12. 25GbE NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 25GbE (25G-1) with RSFEC(528,514), Single lane Example Demo design using QSFPDD1 agilex-pcie-devkit-25gbe-1-fgt-example-design.zip (21.3 B170) 13. 10GbE NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 10GbE (10G-1), Single lane Example Demo design using QSFPDD1 agilex-pcie-devkit-10gbe-1-fgt-example-design.zip (21.3 B170)0Views0likes0CommentsRe: What is source clock of rx_core_clkout of Serial Lite IV IP
Hi, As I understand it, you have some inquiries related to the RX recovered clock port port of the F-Tile Serial Lite IV IP. As I checked the F-Tile Serial Lite IV Intel® FPGA IP User Guide, it seems like there is no RX recovered clock output port supported in this IP. Sorry for the inconvenience.37Views1like0CommentsRe: Where is High Speed Transceiver Demo Design in FPGA Wiki ?
Hi TSUGI, Sorry for the delay. Seems like there is a glitch with the system recently which is causing issue for me to add new post. For your information, I managed to locate a few S10 Superlite IV design links after consulting the admin. Would you mind to check if you are able to download them using the following links? Please let me know if there is any concern. Thank you. 6. Superlite IV (using Native PHY) (with FEC) PAM4 Updated (27/04/2021) Stratix 10 TX SI Board (Prod) : 1.8Tb Superlite IV Demo design using 18 times 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (+ I2C) (Native PHY + KPFEC) S10TX-SIBoard-SuperliteIV-Etile-18x-2-lanes-53Gbps-Native-Phy-Prod.zip (20.4 B72) (12/02/2019) Stratix 10 TX SI Board (S1) : 100G Superlite IV Demo design using 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 100 Gbps of raw data (Native PHY + KPFEC) s10tx-siboard-superliteiv-etile-2x2-lanes-53gbps-native-phy-dual-qsfp.zip (18.1.1 B263) (17/04/2019) Stratix 10 TX SI Board (S1) : 400G Superlite IV Demo design using 8 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 400 Gbps of raw data (+ I2C & Fan Control + tested with 400G Optics) (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_1x8_lanes_53Gbps_Native_Phy.zip (18.1.2 B277) (13/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_1x12_lanes_53Gbps_Native_Phy.zip (18.1.1 B263) (08/03/2019) Stratix 10 TX SI Board (S1) : 1.8Tb Superlite IV Demo design using 3 times 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_3x12_lanes_53Gbps_Native_Phy.zip (18.1.2 B277) NRZ (19/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 24 lanes at 25.78125 Gbps with NRZ encoding and RS-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC) S10TX_SIBoard_SuperliteIV_Etile_1x_24_lanes_26Gbps_Native_Phy.zip (18.1.1 B263)0Views0likes0CommentsRe: Enabling DFE Adaptation on Cyclone 10 GX
Hi, Sorry for delay. There seems to be some glitches in the system which causes some issues for me to add post. Thank you for reaching out. Based on my understanding on the current observation, the Transceiver Toolkit seems to be accessing internal DFE registers, which are not formally exposed for user access. Since DFE adaptation is not officially supported, I’m unable to enable this feature. If you would like to explore this further, I recommend engaging your local sales representative, who can work with our factory team on your request. Please note that this process typically requires sufficient business justification. Regarding your PMA analog tuning in Toolkit, just to check, if you perform auto-sweep with the equalization features (apart from DFE), does it help to find an optimal settings with low BER? Feel free to let me know if you have any questions or need additional clarification. Thank you for your understanding.4Views0likes0CommentsRe: Enabling DFE Adaptation on Cyclone 10 GX
Hi, Sorry for the delay. As I searched through the Cyclone 10 XCVR user guide, seems like I am unable to locate any specific info on the support of the DFE adaptation in C10 GX devices. As I checked with the C10 GX Native PHY, seems like there is no specific DFE adaptation feature as well. For your information, I have also come across one of the previous community post which seems to explain that there is no official DFE adaptation support in C10 GX devices at (https://community.altera.com/discussions/fpga-device/how-can-i-set-the-dfe-decision-feedback-equalization-in-adaptive-mode-for-the-10/204374) Based on these, it seems like there is no official support of DFE adaptation in C10GX XCVR. Sorry for the inconvenience.19Views0likes0CommentsRe: Transceiver data corruption
Hi, One possible cause of intermittent bit errors could be related to signal integrity issues. Have you had a chance to enable serial loopback and check if the issue persists? This step can help isolate whether the problem is due to signal integrity or something else.41Views1like0Comments