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dncmrc1's avatar
dncmrc1
Icon for New Contributor rankNew Contributor
24 days ago
Solved

Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)

We are using a Stratix 10 L-Tile/H-Tile Transceiver Native PHY to implement a DisplayPort TX and RX. The transceiver is set as Basic (Enhanced PCS), TX/RX Duplex. The TX PMA is set as Non bonded, wi...
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  • CheepinC_altera's avatar
    CheepinC_altera
    2 days ago

    Hi,

     

    After consulting with our DisplayPort (DP) IP experts, it appears that our DP is currently not operating in bonded mode for multi‑lane support. You may want to explore our DP IP.

     

    Please let me know if you have any questions or concerns. Thank you.

dncmrc1's avatar
dncmrc1
Icon for New Contributor rankNew Contributor
15 days ago

Hi,

It looks like bonding is not supported at rates > 17.4G:

Also the ATX PLL refuses to configure for 20G with bonding:

Can you please help?

Regards

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 days ago

Hi,

 

Thank you for your question. From your description, you are asking about the maximum data rate supported by the Stratix 10 ATX PLL when operating in bonded mode. You are correct — according to AN 778: Intel® Stratix® 10 L‑Tile/H‑Tile Transceiver Usage, channel bonding is not supported for data rates above 17.4 Gbps. We understand this may be inconvenient, and we appreciate your patience.

 

In parallel, I am consulting with our DisplayPort IP experts to confirm whether the DP IP can support 20 Gbps while using bonded channels. I will update you as soon as I receive a definitive response.

 

If you do not hear back from me by the end of next week, please feel free to ping me. Thank you.