Fitter cannot ...
I am trying to set up a basic SDI transmitter on an Agilex 5. Currently, my setup is a 148.5 MHz refclk, a GTS PMA Direct PHY IP configured for 12G SDI, a GTS Reset Sequencer, and a GTS System PLL configured to take in the refclk and output 742.5 MHz (this is based on the minimum system PLL frequency recommendation in the SDI II IP documentation). I have my serial output differential pair on pins BE129 and BE126 which are the GTS Left 1B TX 0 channels, and my refclk coming in as a differential pair on pins AY120 and AY115 which are the refclk pins for GTS Left 1B. According to the documentation for the SoM, these refclk pins should be configured to 148.5 MHz. For some reason, when I try to compile, the fitter fails in the plan stage with error 14566 "The Fitter cannot place 1 periphery component due to conflicts with existing constraints (1 I/O pad). Fix the errors described in the submessages, and then rerun the Fitter." The submessages read, "Illegal constraint of I/O pad to the location PIN_AY115" (175019), "No legal location could be found out of 1 considered location. Reasons why each location could not be used are summarized below:" (16234), "There is no routing connectivity between the I/O pad and the destination I/O input buffer" (175006), "The I/O pad could not be placed in any location to satisfy its connectivity requirements" (175022), and "The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements" (175022). There isn't very much logic surrounding the system (basically just a counter to create some dummy input data), so I'm not sure why it wouldn't be able to connect specifically the n side of the refclk. Has anyone encountered similar issues/errors and could maybe point me in the right direction? Any help would be appreciated.
Enabling DFE Adaptation on Cyclone 10 GX
Hello! I'm trying to set the DFE Mode to "Adaptation Enabled" on my Cyclone 10 GX processor using the NiosV processor I have in the Cyclone 10. I'm able to turn on the transceivers and detect error bits due to the fact that I'm running at max speed (12.5gbps), but I need to enable DFE adaptation in order to get my error bitrate to decrease. I've been testing using the transceiver toolkit, so I know it is possible, but I haven't been able to find any documentation on how to do this in the Cyclone 10. I have found this page for the Arria 10 (which is, from my understanding, very similar), but these steps have not enabled DFE Adaptation in my testing. I have been using a mix of the Arria 10 register map and the Cyclone 10 register map to get to this point. Any help or insight you have to help me enable DFE adaptation from the NiosV processor would be greatly appreciated!
Stratix-10G FPGA Transceiver Configuration for Ethernet MAC 100G Controller
Hi, We need to validate our custom built Ethernet MAC 100G controller core on Stratix-10G FPGA. We are planning to use the in-built FPGA transceiver for the PHY functionality. From the IP catalog, we selected "L-Tile/H-Tile Transceiver Native PHY Stratix 10 IP" and tried to configure for Ethernet MAC 100G. But we couldn't find any preset configuration which supports either 100G or 25G line rate. Could you pl. suggest what preset configuration to be used? Pl. note that our Ethernet MAC 100G controller core supports 256-bit data path. Thanks, Sunil
Agilex 5 GTS Supported Protocols
Hi Altera/Community, I’m trying to better understand the protocols supported by the Agilex 5 GTS transceivers. In the user guide, it mentions that the supported protocol is 10GBase-LR. I wanted to confirm: is 10GBase-R the underlying protocol used before the optical module? Also, does this mean that other optical modules, such as 10GBase-SR, are supported as well? Any clarification on how the transceivers interact with different optical modules would be greatly appreciated. Thanks in advance!
GTS System with NIOS & MSGDMA
We have a design that we are running on a Premium Agilex 5 development board where we are trying to test an external optical transceiver. We have created a design(NIOS+MSGDMA+GTS) in accordance to the GTS data sheets and have successfully run the Quartus Toolkit to Transmit and Receive data as well as inject errors. We have written firmware that has been able to set up the Tx MSGDMA correctly and we have monitored its signals on Signal Tap and have successfully recorded Start of packet, End of Packet and addresses. However we have not managed to read any of the data received on the Rx MSGDMA. In fact we are not sure if any of the data got sent out by the GTS or even if any of the streaming data was Rx by the GTS ? If someone could try to help us with this debug it would be greatly appreciated !
About the System PLL in Agilex 5
Regarding the System PLL in Agilex 5, the reference clock input can be supplied not only from the dedicated transceiver input pins but also from HVIO pins. However, when assigning the pins, the following Critical Warning occurs. Critical Warning(24190): User has specified a QSF location assignment to drive XPIN_GTS_CLK[0] using PIN_BK19. The PIN_BK19 is on HVIO bank and is not optimal for HSSI PLL refclk usage. Try to use the HSSI native local/global refclk IO instead. Additionally, this HVIO location assignment could cause the Reset Sequencer to be placed into a invalid shoreline. To avoid this, besides the PLL refclk, you must also specify location assignment for the UX native refclk. Is the operation acceptable, and what are the jitter characteristics? Also, are there specific ways to address the Critical Warning?
Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000
Hi, we are using an Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* IP Core. During our tests we noticed some illegal PCIe packages generated presumable due to a wrong data length. We could tackle down the problem to the following basic setup: avalon_mm_master => 128 bit bus => PCIe-Core When we send the following sequence (two words), we get an illegal/unexpected PCIe transfers/behavior: burstcount = 2, address = address_a, data = some_data, byteenable=16'h0000 burstcount = 1, address = address_a+16, data=some_data, byteenable=16'hFFFF When we only send the second word everything works fine. This sequence originally comes from a qsys autogenerated 256=>128 width change in the interconnect somewhere upstream in our project. My question is: Do we miss something here? Does the IP-Core not allow for a first word to be completely disabled? If so, is there any (automatic) way to tell qsys / the interconnect to discard a leading all_bytes_disabled word? 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals Best regards, Michael
