transceiver

52 Topics

Serial IO GPIO Host Controller - INT34BB
Hello, I would like to use the Intel GPIO controller in our applications that are written in .net. I have a motherboard with this controller, I have the pins wired out and I have the driver - but I cannot find any API or any information regarding how I can access this controller (or the pins) programmatically. Does anyone know where I can find a .net API, or any api or documentation for this? Thanks, Yanky
YHers
2 years ago Place FPGA Device
23KViews
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7Comments
UART Core IP (RS-232 Serial Port)
I am having issue with UART (RS-232 Serial Port) Intel FPGA IP v19.2.0 generation on Quartus pro 22.4. The the RX path dose not receive any data. Generated code for the core seams wrong in module "dproc_qsys_uart_0_altera_avalon_uart_1920_tpslhhy_rx_stimulus_source" see attached generated code. Replacing UART Core IP with Uart LW IP solves the problem so I will rule out wrong connections on my part.
dtopou1
3 years ago Place IP & Transceiver
4.2KViews
0likes
13Comments
Cyclone 10 GX Simulation Files
Certain ports and attributes are missing in the simulation outputs. On our current project we use Onespin to verify that the output does things consistently. We have differential IOs in the project however, the output from the simulation file in Quartus doesn't have the attribute differential_mode. So Onespin is telling us that the output of Quartus's simulation file isn't equivalent the input file because of the differential_mode. We use a two step verification process we validate the original against the simulation output, then we validate the previous simulation output versus the current simulation output. On the cyclone10gx_vsd, the port muxsel doesn't show up unless if it is used, Quartus has never done this previously.
Solved
MKwiec
2 years ago Place IP & Transceiver
2.4KViews
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13Comments
Generic Serial Flash Interface reading only 0's
Hi, I'm using the Cyclone 10 EVAL kit with the EP128A flash connected. I perform the following events and made sure that the csr /mem wait requests were low before issuing the next command, but only get all 0x00 for read responses (Signal Tap screenshots are attached): WR ENABLE: csr_addr: 0x07 csr_wr_data: 0x00000006 csr_addr: 0x08 csr_wr_data: 0x00000001 SECTOR 0 ERASE: csr_addr: 0x07 csr_wr_data: 0x000003D8 csr_addr: 0x09 csr_wr_data: 0x00000000 csr_addr: 0x08 csr_wr_data: 0x00000001 WR 4 BYTES OF DATA TO ADDR 0x4000: csr_addr: 0x04 csr_wr_data: 0x00000000 csr_addr: 0x00 csr_wr_data: 0x00000001 csr_addr: 0x06 csr_wr_data: 0x00000502 mem_addr:0x4000 mem_wr_data: 0x0011223 mem_addr:0x4000 mem_wr_data: 0x44556677 mem_addr:0x4000 mem_wr_data: 0x8899AABB mem_addr:0x4000 mem_wr_data: 0xCCDDEEFF READ DATA BACK: csr_addr: 0x04 csr_wr_data: 0x00000000 csr_addr: 0x00 csr_wr_data: 0x00000001 csr_addr: 0x05 csr_wr_data: 0x00000001 mem_addr:0x4000
Solved
Jcole
2 years ago Place IP & Transceiver
2.3KViews
0likes
5Comments
Which FPGA IP can be used FREE in production with the Quartus LITE dev. sw?
We are a small business startup evaluating the the viability of using Altera lower cost FPGAs for small scale production, probably focusing on MAX 10 FPGA, Cyclone IV E, and/or Cyclone V A9. We are using VHDL. One issue is the possible use of (some, if any) IP in production without buying a license. Any IP available for free use in production? (We already know that some IP can be evaluated for free, but need paid licences in production.) We have already established that VHDL 2008 will not be available in the Quartus Lite version, so no cores depending on that is usable for us now. Thanks.
Solved
SmallBusinessOwner
2 years ago Place IP & Transceiver
2.3KViews
0likes
10Comments
eSPI agent core, memory write and memory read access
Hi, I want to use Intel eSPI agent core in MAX10 device for accessing general addresses. Can I use peripheral channel with memory read(32-bit) and memory write(32-bit) for accessing the user defined addresses (or) Is it meant only for accessing the "PORT IO addresses " like port80 ? Could anyone confirm on this Regards Theja
Theja
3 years ago Place IP & Transceiver
2.1KViews
0likes
6Comments
Configuring a PLL
I am using a Cyclone iii device and I have an interface to an Imaging sensor that receives MIPI outputs. ONE CLOCK LINE ONE SYNCHRONIZATION LINE FOUR IMAGE LINES Cyclone III has a core speed limit of 250MHz. However, the SERDES should be able to read in serial data at much higher rates. IS THIS ASSUMPTION CORRECT. As an experiment - I want to use the PLL to read in the synchronization line- using the scandata and scanclk inputs. Is this a correct way for implementing a Serdes? What is the relationship between the INCLK0 and the SCANCLK input. I have tried using the ALT_Rx and ALTPLL separately and always run into timing violations at high speeds (360MHz). I can close timing at up to 250MHz. What is the best way to go about implementing a SERDES in FPGAs. (1) An ALTPLL + {ALT_Rx for all lines} or (2) ALTPLL with scan clk and scandata line for the synchronization line + ALT_Rx for the Image lines?
Solved
UMall1
2 years ago Place IP & Transceiver
2KViews
0likes
5Comments
Generic Serial Flash Interface addressing only generating 22 bit addressing for 24 bit flash
New to using some of the Avalon based cores. I generated a 128MB Generic Serial Flash Interface core for my EPCQ128A Flash, the addressing is only Avalon memory is section is 22 bits, but how do I sent my 24-bit address to the core to send to the flash? Am I missing a correlation between the value sent to the Avalon memory and the Flash memory?
Solved
Jcole
2 years ago Place IP & Transceiver
1.9KViews
0likes
5Comments
Request for an official email to declare Intel acquired structured eASIC company.
Our company want to send an quotation to eASIC company before, but found that Intel acquired structured ASIC company eASIC into Programmable Systems Group (PSG). Could you please send us an official email to declare this situation for our record, thank you.
HH128
2 years ago Place IP & Transceiver
1.8KViews
0likes
3Comments
Serial Lite III "start_of_burst" and "end_of_burst"
I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work requires driving the valid_tx signal discontinuously ( as I don't always have data to send ). However, the data itself isn't segmented into packets and doesn't have a defined "start" or "end". Question: Can I tie start_of_burst_tx and end_of_burst_tx to GND
host
3 years ago Place IP & Transceiver
1.8KViews
0likes
8Comments