Forum Discussion
Occasional ContributorConfiguring a PLL
I am using a Cyclone iii device and I have an interface to an Imaging sensor that receives MIPI outputs.
ONE CLOCK LINE
ONE SYNCHRONIZATION LINE
FOUR IMAGE LINES
Cyclone III has a core speed limit of 250MHz. However, the SERDES should be able to read in serial data at much higher rates. IS THIS ASSUMPTION CORRECT.
As an experiment - I want to use the PLL to read in the synchronization line- using the scandata and scanclk inputs. Is this a correct way for implementing a Serdes?
What is the relationship between the INCLK0 and the SCANCLK input. I have tried using the ALT_Rx and ALTPLL separately and always run into timing violations at high speeds (360MHz). I can close timing at up to 250MHz.
What is the best way to go about implementing a SERDES in FPGAs.
(1) An ALTPLL + {ALT_Rx for all lines} or
(2) ALTPLL with scan clk and scandata line for the synchronization line + ALT_Rx for the Image lines?
Hello,
From the device handbook, it mentioned that the Cyclone III device family does not
contain dedicated serialization or deserialization circuitry. Therefore, shift registers,
internal phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. The differential interface data serializers and deserializers (SERDES) are automatically constructed in the core logic elements (LEs) with the Quartus® II software ALTLVDS megafunction.
5 Replies
FvMSuper Contributor
Hi,
I don't understand all details of your interface, specifically I'm not aware of "synchronization line" playing a role in MIPI camera interface. As far as I know, MIPI is using serial data rates above 1 GBPS per lane. Maximal data rate achievable with Cyclone III SERDES is 875 MBPS (depending on FPGA speed grade). Therefore it can't receive MIPI data.
UMall1I am using an On Semi chip - the rate is 720Mbps. The synchronization line carries readout state - Frame Start, Line start, Frame end, Line End, CRC, Image etc. When I design the PLL I see that - despite having Cyclone III as the implementation chip - Quartus shows a - "Can implement Interface" message. I use the Cyclone III EP3C80F484C6 FPGA. 720Mbps seems to be well within the chip's abilities.
AqidAyman_AlteraRegular Contributor
Hello,
From the device handbook, it mentioned that the Cyclone III device family does not
contain dedicated serialization or deserialization circuitry. Therefore, shift registers,
internal phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. The differential interface data serializers and deserializers (SERDES) are automatically constructed in the core logic elements (LEs) with the Quartus® II software ALTLVDS megafunction.
- AqidAyman_Altera
Hello,
I wish to follow up with you on this issue,
Is there any more support needed?
Regards,
Aqid
- AqidAyman_Altera
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.
