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UMall1's avatar
UMall1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Configuring a PLL

I am using a Cyclone iii device and I have an interface to an Imaging sensor that receives MIPI outputs. ONE CLOCK LINE ONE SYNCHRONIZATION LINE FOUR IMAGE LINES Cyclone III has a core speed limi...
Transceiver
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    2 years ago

    Hello,


    From the device handbook, it mentioned that the Cyclone III device family does not

    contain dedicated serialization or deserialization circuitry. Therefore, shift registers,

    internal phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. The differential interface data serializers and deserializers (SERDES) are automatically constructed in the core logic elements (LEs) with the Quartus® II software ALTLVDS megafunction.


FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
I don't understand all details of your interface, specifically I'm not aware of "synchronization line" playing a role in MIPI camera interface. As far as I know, MIPI is using serial data rates above 1 GBPS per lane. Maximal data rate achievable with Cyclone III SERDES is 875 MBPS (depending on FPGA speed grade). Therefore it can't receive MIPI data.

  • UMall1's avatar
    UMall1
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I am using an On Semi chip - the rate is 720Mbps. The synchronization line carries readout state - Frame Start, Line start, Frame end, Line End, CRC, Image etc. When I design the PLL I see that - despite having Cyclone III as the implementation chip - Quartus shows a - "Can implement Interface" message. I use the Cyclone III EP3C80F484C6 FPGA. 720Mbps seems to be well within the chip's abilities.