Configuring a PLL

Hello,

From the device handbook, it mentioned that the Cyclone III device family does not

contain dedicated serialization or deserialization circuitry. Therefore, shift registers,

internal phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. The differential interface data serializers and deserializers (SERDES) are automatically constructed in the core logic elements (LEs) with the Quartus® II software ALTLVDS megafunction.