Agilex 7 I Series Development Kit: External hardware access error when programming
I have a compiled design that I would like to test that implements Ethernet on F-Tile. When I try to program the FPGA with my bitstream, it stops and prompts me with the following errors: Would anyone know how to fix this or have insight on why this is happening?
Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5
Hello, According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Center), the RMS jitter integrated from 10 kHz – 20 MHz, including spurs, is indicated as 522fs (maximum value). We are using in our design a 156.25MHz clock (AX3DAF1-156.2500 from abracon), and the measured jitter is ~1ps currently. We would like to know if this specification is for specific performances or if it’s a strict specification. (in our case, it’ll be for a 1G operation) Thanks, Best RegardsF-tile 10GBASE-R firecode FEC IP (Agilex 7)
Hi! We require to support 10GBASE-R clause 74 (firecode) FEC + PCS. This option isn't available in the Agile 7 F-Tile hard FEC IP. It is available for 25G rates, but we need it specifically for 10G. Our application doesn't require a MAC, in other rates we are to use PCS/MII mode It seems the only way forward is a soft firecode FEC + PCS, which would could connect to our FGT in PMA direct mode. Is this correct, and does altera provide an equivalent soft IP in order to support this configuration?
Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted
Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file? A set of pin locations and IO standard settings for the AXE5 Eagle would be optimal, but any other dev kit would be helpful. According to the "GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs" (848477) page 29 under "Target Development Kit Tab" is says: "Target development kit option specifies the target development kit used to generate the project. Ensure the pin assignments in the .qsf file are appropriate." But it seems like this will only set the BOARD parameter in the resulting qsf, e.g. when using the Premium Development Kit it results in the following addtion to the qsf file: set_global_assignment -name BOARD "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1" which results in no location or IO standard settings in the qsf and I/O Assignment Warnings in the fitter report after the build: +-----------------------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; o_tx_serial_data[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; o_tx_serial_data_n[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_lowpwr ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_rstn ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; i_reconfig_clk ; Missing I/O standard ; ; i_rx_serial_data_n[0] ; Missing I/O standard ; ; i_rx_serial_data[0] ; Missing I/O standard ; ; i_clk_ref_p ; Missing I/O standard ; ; o_tx_serial_data[0] ; Missing location assignment ; ; o_tx_serial_data_n[0] ; Missing location assignment ; ; qsfp_lowpwr ; Missing location assignment ; ; qsfp_rstn ; Missing location assignment ; ; i_reconfig_clk ; Missing location assignment ; ; i_rx_serial_data_n[0] ; Missing location assignment ; ; i_rx_serial_data[0] ; Missing location assignment ; ; i_clk_ref_p ; Missing location assignment ; ; i_refclk2pll_p ; Missing location assignment ; +-----------------------+-----------------------------------------------------------------------------------------------+ Whenever I try to assign these myself I get errors like Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IPFLUXTOP_UXTOP_WRAP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 IPFLUXTOP_UXTOP_WRAP, which is within GTS Ethernet Hard IP ex_10G_intel_eth_gts_1000_6dyx4dq. or this or other type of layout or clocking type constraint errors: Error (11216): Output port "O_SYSPLL_C0" of "SM_HSSI_PLL_WRAP" cannot connect to PLD port "CLK" of "FF" for node "kr_dut|intel_eth_anlt_gts_0|ip_inst|sip_inst|u_intel_eth_anlt_gts_csr_top|u__intel_eth_anlt_gts_csr_avmm_arb|o_avmm_rdata[0]". It would be nice if I could obtain a set of correct and working pin assignment which actually results in a working sof file so I can try to understand what the actual constraints are. Is there a dev kit as described which the pin assignments are generated or provided or could anybody please provide a set of pin assignments for the above signals for a dev kit? Cheers!PCIe Hard IP - Can 'valid' De-assert Between SOP and EOP During DMA Read Completion?
Product / IP: Intel PCIe Hard IP (Avalon-ST Interface Device Family: Cyclon 10 GX Reference Manual: https://docs.altera.com/r/docs/683647/18.0/arria-10-and-cyclone-10-gx-avalon-streaming-interface-for-pci-express-user-guide/datasheet I am an FPGA Design Engineer currently working on verifying the application layer logic interfacing with Intel's PCIe Hard IP over the Avalon Streaming (Avalon-ST) interface. As part of the verification effort, I have developed an Avalon-ST Bus Functional Model (BFM) that mimics the RX-side behavior of the PCIe Hard IP — specifically, how it presents TLP data (DMA Read Completions) to the downstream application logic. During simulation, my BFM generates scenarios where the 'valid' signal is de-asserted between 'startofpacket (SOP)' and 'endofpacket (EOP)' — i.e., mid-packet gaps or "bubbles" are introduced within a single TLP transfer. When this occurs, the application layer logic does not handle it correctly, causing functional failures. Before proceeding with fixing the application logic to handle this case, I need to confirm from Intel whether this behavior is actually possible on the real PCIe Hard IP hardware Question 1: On the RX Avalon-ST interface, when the PCIe Hard IP is acting as the SOURCE (driving TLP completion data toward user application logic), is it possible for the 'valid' signal to be de-asserted between SOP and EOP within the same TLP packet? Question 2: If yes, under what conditions can this occur? Question 3: Does the Intel PCIe Hard IP Reference Manual explicitly document this behavior anywhere? If so, could you point to the relevant section?
Display port TX SST not working.
Hi, I am working on an existing project where Display Port Transmitter MST (multi stream) is already present and working. In the current version I just need to convert that transmitter into a Dispaly Port TX SST (single stream). The result is that, starting from the design example i got a version which works only up to 3840x2160 30Hz and does not at 3840x2160 60Hz. In both cases the training is completed and lane allocated adt 5.4GHz. Bun in tha case of 60 Hz I do not see any image. The Quartus Prime Pro used is 17.1.2 for Windows. I do not know where to check for debug more. Kind Regards, Paolo.
F-Tile xcvr placement on DK-DEV-AGF023FA
I have an Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF023F. I have 1 F-Tile working with PCIe Gen4x16, and want to use the second for 400Gb Ethernet. I have used the F-Tile channel placement tool, which results in a valid placement. See attached. I have been plagued with placer message such as the following. Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 400g block but the location only supports stream(s) [7, 11, 13, 14]. I have swapped bit orders and other trials, and they all lead to a similar error. Given the placement of the QSFPDD on the board, I need to used FGT Quads 2 and 3 I have also tried to use the 100G-4 F-Tile configuration, which move the FGT usage to Quad 1. And I result it the following error: Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 100g block but the location only supports stream(s) [1, 2, 3]. I have tried the example design, changing the device to the above board, but the build fails. Using Quartus 25.3.0 What is needed to move past these errors? Thanks, Ed.
