Agilex5: How to use a GTS refclk to clock the FPGA fabric?

I tried to use the GTS System PLL configured with FABRIC_USE_CASE and ref clock frequency to 156.25MHz, C1 enable and selected 101.768092 MHz from the C1 output frequency menu but this results in the following error:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
    Error (175019): Illegal constraint of I/O pad to the location PIN_AT120
        Info (14596): Information about the failing component(s):
            Info (175028): The I/O pad name(s): pad_spf_refclk_p
        Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
            Error (175006): There is no routing connectivity between the I/O pad and destination I/O input buffer
                Info (175027): Destination: I/O input buffer pad_spf_refclk_p~input
                Error (175022): The I/O pad could not be placed in any location to satisfy its connectivity requirements
                Error (175022): The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements
                Info (175029): 1 location affected
                    Info (175029): PIN_AT120

PIN_AT120 is REFCLK_GTSL1C_RX_P on the Arrow AXE5-Eagle board.

I also tried to use the regular IOPLL but it results in the same error.

How can I use the GTS refclk to clock the FPGA fabric?