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zener's avatar
zener
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
Solved

Agilex5: How to use a GTS refclk to clock the FPGA fabric?

I tried to use the GTS System PLL configured with FABRIC_USE_CASE and ref clock frequency to 156.25MHz, C1 enable and selected 101.768092 MHz from the C1 output frequency menu but this results in the...
Transceiver
  • FvM's avatar
    FvM
    3 months ago

    Hi,
    posted minimal design doesn't work because it doesn't connect system PLL output to anything, thus the PLL is discarded during synthesis.

    Modified top.sv respectively

        assign {//pad_rled0,
            pad_gled0,
            pad_bled0,
            pad_rled1,
            pad_gled1,
            pad_bled1,
            pad_rled2,
            pad_gled2,
            pad_bled2,
            pad_rled3,
            pad_gled3,
            pad_bled3} = 11'o213; //12'o4213;

      assign pad_dbg_tx = pad_dbg_rx;
		assign pad_rled0 = clk101p768092;
		assign clk101p768092_ready = 1'b1;


    Connecting the PLL reveals another error. The fact that you never got to this point suggests that the PLL wasn't implemented in your design, e.g. due to missing connectivity.

    Error(22849): Intel FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ, or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file.

    Added

    set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ

    Get still complains about missing constraints, but design basically compiles now.

    Regards
    Frank

    P.S.: Don't know, if DEVICE_INITIALIZATION_CLOCK is actually required to run system_pll. GTS PHY itself needs it according to device handbook.

zener's avatar
zener
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
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Pasting the above into 'cat | base64 -d | xz -dc > gts_system_pll.ip' should result gts_system_pll. ip with an md5sum of e0eeb0ab0cd45da5eb19b385cef0ca56.