Clarification on TX/RX P&N Invert feature support in TSE IP core
Hello, Based on the page below from the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs (version 25.1, “Analog Parameter Options” section), the “Enable TX P&N Invert” and “Enable RX P&N Invert” options are described as preliminary and not supported in hardware: 3.3.11. Analog Parameter Options However, according to the updated page for version 25.1.1, those same features are now marked as supported in hardware: 3.3.11. Analog Parameter Options In the Analog Parameters tab of the Triple-Speed Ethernet (TSE) Intel FPGA IP, these TX/RX P&N Invert options also appear as configurable parameters. Could you please confirm whether these features are expected to function in Quartus Prime Pro 25.1.1 and Quartus Prime Pro 25.3 when used in the TSE IP core? Also, could you please let us know what happens if we enable these P/N inversion options in Quartus 25.1, since the documentation indicates that they are not supported in hardware in that release? Thank you in advance for your help and clarification. Best regards,Solved103Views1like8Comments
