eSPI agent core, memory write and memory read access

Hi,

As I understand from the eSPI Specification, any level of peripheral can be accessed by the eSPI Master provided correct chip select decoding happens.

Please go through the spec in detail, especially section 3.2 Architecture Descriptions.

Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms) (intel.com)

Regards

Hi,

Do you have any further queries on this topic?

Regards

Hi,

Thanks for your reply. Actually want to use this espi agent core slave for register read/write access i.e., CPU(host) will access this user defined registers through eSPI. Whether this is possible ?.

It will be great help if you share the example design or test bench or any simulation setup ..

Hi,
The Intel eSPI Agent Core is receiving a PUT_MEMRD32_SHORT (1 byte) packet from the eSPI master. I am reading out the Non-posted RX FIFO('h10) via IP core's Avalon MM bus until RX queue is empty. I am getting the address and like to respond the associated data. So I am writing the following data in the NPTXFIFO (14h) :

- Byte 1: 0Fh (cycle type)
- Byte 2: 00h (length MSB)
- Byte 3: 00h (length LSB)
- Byte 4: 55h (Data)

After that I am writing 02h (NPTXFIFO_AVAIL) to the IP core's Control Register (4h).

But the Agent is only sending DEFER, it doesn't send the response with the data.

Is I am doing in correct way?

Regards

Theja

Hi,

Are you generating the espi_cs_n while giving the commands to the eSPI agent core? It is difficult to tell the exact issue. Request you to send your design so that it can be simulated and checked for issues.

Regards

As there is no response to this case, I am setting it to closure. Please feel free to open a new case.

Regards