7 Results
Can LPDDR5 External Memory Interfaces (EMIF) IP support single VDD2 rail mode in Agilex™ 5 FPGA and Agilex™ 7 FPGA M‑Series devices?
Description No. LPDDR5 External Memory Interfaces (EMIF) IP in Agilex™ 5 FPGA and Agilex™ 7 FPGA M‑Series devices only supports dual VDD2 rail mode. Resolution You need to separate VDD2 power a...Why do I get timing closure failures when compiling the LPDDR5 EMIF Example Design for the Agilex™ 7 M Series or the Agilex™ 5 FPGAs?
Description In Quartus® Prime Pro Edition Software version 24.1, when compiling the LPDDR5 EMIF Example Design for either the Agilex™ 7 M Series or the Agilex™ 5 FPGAs, you will encounter the f...Do DDR5 or LPDDR5 memory interfaces for Intel Agilex® 5 and Intel Agilex® 7 FPGA devices support mailbox commands to all channels for multichannel instances?
Description For Intel Agilex® 5 FPGA and Intel Agilex® 7 FPGA in Intel® Quartus® Prime Pro Edition Software version 23.3, DDR5 2x16 and LPDDR5 2x16 EMIF IP mailbox command "GET_MEM_INTF_INFO" r...Why does Intel Agilex® 7 FPGA LPDDR5 error out in Intel® Quartus® Prime Pro Edition Software version 23.2 with calibration failures?
Description To work around this problem, ignore the error in Intel Agilex® 7 LPDDR5 Mem Device IP when changing the read latency from the auto-computed value from 9 cycles to 10 cycles b...Why does Intel Agilex® 7 FPGA fail with fitter error while accessing HPS EMIF IP with DDR4 2x16, DDR4 2x32, and LPDDR5 2x32 with/without ECC configuration in Intel® Quartus® Prime Pro Edition S...
Description Intel® Quartus® Prime Pro Edition Software version 23.2 does not support Intel Agilex® 7 HPS EMIF IP IP with DDR4 2x16, DDR4 2x32, LPDDR5 2x32 with/without ECC configuration c...