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Why does the Quartus® fail Design Analysis when the 1G/2.5G/5G/10G Multirate Ethernet PHY IP and the F-Tile 1000BASE-KX Ethernet PHY IP are used in the same design?
...P cores in the same project: 1G/2.5G/5G/10G Multirate Ethernet PHY IP (alt_mge_phy) F-Tile 1000BASE-KX Ethernet PHY IP (intel_mge_phy_f) Both IP cores include an RTL module named a...56Views0likes0CommentsWhat are the supported variants for Low Latency Ethernet 10G MAC FPGA IP for Agilex™ 5 FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the Low Latency Ethernet 10G MAC FPGA IP indicates values for parameter Speed as follows: 10G 1G/10G...233Views0likes0CommentsWhy does the Stratix®10 FPGA Low Latency Ethernet 10G MAC IP Example Design simulation fail?
...bsp;10M/100M/1G/2.5G/5G/10G(USXGMII) preset. # ** Error: ../models/altera_eth_top.sv(128): Module 'altera_eth_top_auto_tiles' is not defined. Resolution This problem has be fixed in the Q...128Views0likes0CommentsWhy does the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP 10M/100M/1G/2.5G/10G Ethernet Design Example fail during simulation when using the Cadence* Xcelium* tool?
Description Due to a problem in the Quartus® Prime Pro Edition Software Version 23.3 and earlier, the 10M/100M/1G/2.5G/10G Ethernet Design Example for the Low Latency Ethernet 10G M...113Views0likes0CommentsWhy do I see Siemens QuestaSim* and Cadence Xcelium* simulation failure for the F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example?
Description Due to an issue with the Quartus® Prime Pro Edition software version 25.3.1, you may see ModelSim*– FPGA Edition and Xcelium* simulation failures for F-Tile 10M/100M/1G/2.5G/5G/10G (U...59Views0likes0CommentsWhy does the F-Tile Low Latency Ethernet 10G MAC FPGA IP show the target development kit as a P-Tile and E-Tile board?
Description Due to a problem in the Quartus® Prime Pro Edition Design Software Version 24.2, the F-Tile Low Latency Ethernet 10G MAC FPGA IP GUI Example Design tab shows the target board as A...214Views0likes0CommentsWhy are my AXI-Lite register accesses to the PTP packet parser of the Ethernet Subsystem IP failing in 10G Asynchronous Clocking Mode?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, AXI-lite register accesses to the PTP packet parser of the Ethernet Subsystem IP will fail in 10G Asynchronous C...134Views0likes0Comments