109 Results
Why do I see Siemens QuestaSim* and Cadence Xcelium* simulation failure for the F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example?
Description Due to an issue with the Quartus® Prime Pro Edition software version 25.3.1, you may see ModelSim*– FPGA Edition and Xcelium* simulation failures for F-Tile 10M/100M/1G/2.5G/5G/10G (U...39Views0likes0CommentsWhat are the supported variants for Low Latency Ethernet 10G MAC FPGA IP for Agilex™ 5 FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the Low Latency Ethernet 10G MAC FPGA IP indicates values for parameter Speed as follows: 10G 1G/10G...108Views0likes0CommentsWhy does the Stratix®10 FPGA Low Latency Ethernet 10G MAC IP Example Design simulation fail?
...bsp;10M/100M/1G/2.5G/5G/10G(USXGMII) preset. # ** Error: ../models/altera_eth_top.sv(128): Module 'altera_eth_top_auto_tiles' is not defined. Resolution This problem has be fixed in the Q...47Views0likes0CommentsWhy does the F-Tile Low Latency Ethernet 10G MAC FPGA IP show the target development kit as a P-Tile and E-Tile board?
Description Due to a problem in the Quartus® Prime Pro Edition Design Software Version 24.2, the F-Tile Low Latency Ethernet 10G MAC FPGA IP GUI Example Design tab shows the target board as A...84Views0likes0CommentsWhy does the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP 10M/100M/1G/2.5G/10G Ethernet Design Example fail during simulation when using the Cadence* Xcelium* tool?
Description Due to a problem in the Quartus® Prime Pro Edition Software Version 23.3 and earlier, the 10M/100M/1G/2.5G/10G Ethernet Design Example for the Low Latency Ethernet 10G M...43Views0likes0CommentsWhy are my AXI-Lite register accesses to the PTP packet parser of the Ethernet Subsystem IP failing in 10G Asynchronous Clocking Mode?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, AXI-lite register accesses to the PTP packet parser of the Ethernet Subsystem IP will fail in 10G Asynchronous C...49Views0likes0CommentsWhy is a remote fault insertion failure seen for a 10G using the F-Tile Ethernet FPGA Hard IP, not reaching the sender when the sender’s transmitter path is broken?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and 24.2, the F-Tile Ethernet FPGA Hard IP shows remote fault not reaching the sender when the s...120Views0likes0CommentsWhy is the o_rx_pfc port enabled for longer durations than normally when generating designs at data rates between 10G-200G using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
...ause signal duration. Resolution To work around this problem, disable the truncation option when PFC is enabled for designs with data rates between 10G-200G using F-Tile Ethernet Hard IP.60Views0likes0Comments