Why does the Stratix®10 FPGA Low Latency Ethernet 10G MAC IP Example Design simulation fail?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.1 or earlier, the following error will appear in the simulation when using the design example generated by the 10M/100M/1G/2.5G/5G/10G(USXGMII) preset.

# ** Error: ../models/altera_eth_top.sv(128): Module 'altera_eth_top_auto_tiles' is not defined.

Resolution

This problem has be fixed in the Quartus® Prime Pro Edition Software version 23.2.