Why does the system report an error when generating rbf from sof files and fsbl files?

Error message:

Error: Internal Error: Sub-system: BITASM, File: /quartus/pgm/bitasm/bitasm_common_code.cpp, Line: 518 HPS data start address(-1950584) is not 16 aligned

Device and tool information：

1. The device used is Stratix 10 1SX110HN2F43I2VG, without using the Stratix 10 SoC Development Kit；
2. Quartus Prime Pro25.1.1
3. U-boot source code：u-boot-socfpga-socfpga_v2025.04
4. ATF source code：arm-trusted-firmware-socfpga_v2.13.0

Operation steps：

1. Simplified the Platform Designer section of the Stratix 10 GHRD project；
2. 【Device and Pin Options】->【Configuration】Set the HPS/FPGA configuration order to be HPS First；
3. The Quartus full compilation generates the sof file in the "output_files" directory；
4. Compile the ATF source code, and obtain the bl31.bin file in the path of ./build/stratix10/release；
5. Copy the bl31.bin file to the root directory of u-boot, compile the u-boot source code, and obtain the u-boot-spl file in the ./spl/ directory；
6. Convert u-boot-spl to u-boot-spl.hex and copy it to the output_files directory；

7. Open the Programming File Generator tool and configure the Output Files：

   
8.  Configure Input Files, add sof and HEX files：

   9. Configuration Device：

   

   10. Generate error：