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Motaz_sami's avatar
Motaz_sami
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2 months ago

U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation

I am reaching out for technical assistance regarding a reproducible boot failure on the Terasic Atum A5 Rev B development board (Agilex 5) when using Quartus Prime Pro 24.3.

I am attempting to compile a custom design that utilizes the Lightweight HPS-to-FPGA (lwhps2fpga) bus. My current workflow is as follows:

Compile the project in Quartus 24.3 to generate the .sof file.

Merge the .sof with the official Terasic FSBL .hex file.

Use the Programming File Generator (PFG) to create a .jic file.

Flash the .jic to the QSPI.

The Issue:

When flashing the .jic generated by this workflow, the boot process fails during the main U-Boot phase. The U-Boot SPL and ATF (BL31) load successfully. However, after U-Boot attempts to load the environment, the system crashes with a "Synchronous Abort" handler (esr 0x96000010, far 0x108d2000). This triggers a CPU reset with the message ### ERROR ### Please RESET the board ###.  

(I have attached the full UART terminal log of the boot sequence for reference).

Isolation Testing:

To isolate the issue from my custom logic, I applied this exact same compilation and .jic generation workflow to the official Terasic GHRD bundled with the board. The result was identical—the GHRD .jic generated by Quartus 24.3 crashes at the exact same U-Boot Synchronous Abort.

Conversely, when I bypass compilation and simply flash the original, pre-compiled .jic provided in the Terasic resource package, the board boots into Linux flawlessly. This confirms the physical hardware is fully functional and the issue is strictly isolated to the .jic files being generated by the 24.3 workflow.

Questions:

Is there a known issue or missing step in the Quartus 24.3 workflow when merging the FSBL or configuring the .jic for the Agilex 5 that would cause U-Boot to encounter a Data Abort (likely when probing the AXI bridges)?

What are the exact PFG parameters or required patches to successfully generate a booting .jic for this board under the 24.3 release?

I look forward to your guidance on resolving this workflow issue

Arm Processor
general
Hps Boot

8 Replies

  • Motaz_sami's avatar
    Motaz_sami
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    1 month ago

    The problem has been solved. The root cause turned out to be a version mismatch in my system's path environments. I had originally been working on Quartus 26.1 and subsequently moved to version 24.3 to align perfectly with the official Terasic GHRD. However, when I downgraded, my environment variables did not update to reflect the change. Consequently, whenever I ran any scripts or batch files, they were still executing using the 26.1 toolchain in the background. This silent version mixing corrupted the workflow and caused the Synchronous Abort during the main U-Boot phase.

    Thankfully, after correcting the environment variables to point strictly to the 24.3 installation, the workflow completes successfully and the board boots into Linux.

    However, I am now facing a secondary configuration issue. After the system boots, I cannot access or use any bus (including the lwhps2fpga bus) by default. The only way I can interact with the custom logic is if I interrupt the boot sequence, drop into the U-Boot bash shell, and manually execute the bridge enable command.

    Could anyone explain why the AXI bridges are remaining disabled by default after configuration? What is the recommended method or required modification to the environment so that U-Boot or Linux automatically enables these bridges during the standard boot flow

  • JamesG_Altera's avatar
    JamesG_Altera
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    2 months ago

    I have some questions about the process you have followed:

    • What command did you use to merge the .hex with the SOF? Did you use the command found in sof_with_hps.bat supplied by Terasic?
    • What command did you use to generate the JIC file from the SOF? Did you use the command found in sof_to_jic.bat supplied by Terasic?
    • Your U-boot SPL comes from the hex file supplied by Terasic, in the GHRD source tree. But where does your full U-Boot software come from? 

     

    • Motaz_sami's avatar
      Motaz_sami
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      1 month ago

      Everything I used was the standard ,that shipped with the board from terasic

    • kbrunham_altera's avatar
      kbrunham_altera
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      1 month ago

      Hello,

      24.3 is very early software for Agilex 5. I would strongly recommend updating to 26.1 and then using the validated ATF and Uboot ingredients from https://github.com/altera-fpga with the label QPDS26.1_REL_GSRD_PR

       

      • Motaz_sami's avatar
        Motaz_sami
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        1 month ago

        I was using 26.1 but had to downgrade to 24.3 to be able to use the Terasic GHRD because any other version causes a lot of issues with it