Wireless Transmission using Cyclone II FPGA (Verilog HDL)

Please describe your problem a little bit more concrete?

What is the purpose of your design?

Are you making a Radio Transceiver?

What do you do with the 8 bits output and 4 bits input?

What is your setup?

What is your coding?

What is it that you want to know?

data that is to be sent from the DE1 board is ASCII codes and morse codes

whereas the encoder only has 4 data pins

how to divide the 8-bit data into 4-bit so that it can be sent twice?

and what about the receiver part?

how to store the received data and combine it again into the 8-bit data?

What physical medium are you targeting with your "Wireless Transmission"? Is this sound, infra-red, light, RF or what???

For splitting up 8 bits into two 4 bit words you should simply take the first 4 bits and then the last four bits.

e.g.

...
reg  output_data;
wire  first_four, last_four;
 
assign first_four = output_data;
assign last_four = output_data;
...

I'm using RF transmission.

The data is in ASCII code form, which is 8-bit per data.

I now have to separate the 8-bit into 2 four-bits, so that the first 4 bits (LSB) is sent.

Then it will be followed by the other 4 bits (MSB).

But I have tried it using LEDs first.

Once a key is pressed, sometimes the MSB will be received first.

Sometimes, the LSB will be received first.

And, only second time of the key press will trigger the LEDs to change.

Why is it so?

sickmuse:

What kind of RF are you using? What frequency? What modulation (ASK, PSK,..), What standard (Bluetooth, Zigbee...)?

How are you replacing the RF link with LEDs?

To enable members of the forum to help you with this problem, you should be more specific and/or provide the code that does not do what you want it to do.

RF frequency 433.92 MHz

Modulation: FSK

I'm connecting the 4 data pins of the decoder at the receiver side to 4 LEDs.

this is the code for receiver side:

module receive_testing

# (parameter W_SIZE = 2) // 2^W_SIZE word in FIFO

(clk, reset, from_expansion, LED);

input clk, reset;

input [3:0] from_expansion;

output wire [7:0] LED;

reg write_code;

wire full_code, read_code;

reg [7:0] data_out_reg;

wire write_enable, write_disable;

wire [7:0] data_out_next;

fifo# (.B(8), .W(W_SIZE)) fifo_block_unit

(.clk(clk),

.reset(reset),

.write(write_code),

.read(read_code),

.write_data(from_expansion),

.read_data(data_out_next),

.empty(write_enable),

.full());

always @(posedge clk)

if (reset)

data_out_reg = 0;

else

data_out_reg <= data_out_next;

always@*

begin

if(from_expansion)

write_code <= 1;

else

write_code <= 0;

end

assign LED = data_out_reg;

assign read_code = ~write_code;

endmodule

module fifo

# (parameter B=8, W=4)

(clk, reset, read, write, write_data, read_data, empty, full);

input clk, reset, read, write;

input wire [B-1:0] write_data;

output empty, full;

output wire [B-1:0] read_data;

// signal declaration

reg [B-1:0] array_reg [2**W-1:0];

reg [W-1:0] write_reg, write_next, write_done;

reg [W-1:0] read_reg, read_next, read_done;

reg full_reg, empty_reg, full_next, empty_next;

wire write_enable;

// body

// register file write operation

always @(posedge clk)

if (write_enable)

array_reg[write_reg] <= write_data;

// register file read operation

assign read_data = array_reg[read_reg];

// write enabled only when FIFO is not full

assign write_enable = write & ~full_reg;

// fifo control logic

// register for read and write pointers

always @(posedge clk, posedge reset)

if (reset)

begin

write_reg <= 0;

read_reg <= 0;

full_reg <= 1'b0;

empty_reg <= 1'b1;

end

else

begin

write_reg <= write_next;

read_reg <= read_next;

full_reg <= full_next;

empty_reg <= empty_next;

end

// next-state logic for read and write pointers

always @*

begin

// successive pointer values

write_done = write_reg + 1;

read_done = read_reg + 1;

// default: keep old values

write_next = write_reg;

read_next = read_reg;

full_next = full_reg;

empty_next = empty_reg;

case ({write, read})

//2'b00: no options

2'b01: // read

if (~empty_reg)

begin

read_next = read_done;

full_next = 0;

if (read_done==write_reg)

empty_next = 1;

end

2'b10: // write

if (~full_reg)

begin

write_next = write_done;

empty_next = 0;

if (write_done==read_reg)

full_next = 1;

end

2'b11: //read and write

begin

write_next= write_done;

read_next = read_done;

end

endcase

end

// output

assign full = full_reg;

assign empty = empty_reg;

endmodule

This is another example codings we've written:

module testing_wed2 (data_in, data_out);

input [7:0] data_in;

output wire [3:0] data_out;

reg lsb_enable;

wire msb_enable;

always@*

begin

if(data_in)

lsb_enable <= 1;

else

lsb_enable <= 0;

end

lsbmo lsbmo_controller_block_unit

(.data_inl(data_in),

.lsb_enable(lsb_enable),

.msb_enable(msb_enable),

.data_outl(data_out));

msb msb_controller_block_unit

(.data_inm(data_in),

.msb_enable(msb_enable),

.data_outm(data_out));

endmodule

module lsbmo(

input [7:0] data_inl,

input lsb_enable,

output reg [3:0] data_outl ,

output reg msb_enable );

always@*

begin

if(lsb_enable)

data_outl = data_inl[3:0];

msb_enable <= 1;

end

endmodule

module msb(

input msb_enable,

input [7:0] data_inm,

output reg [3:0] data_outm

);

always@*

begin

if(msb_enable)

data_outm = data_inm [7:4];

end

endmodule

Error: Net "data_out[3]~0", which fans out to "data_out[3]", cannot be assigned more than one value

Error: Net is fed by "lsbmo:lsbmo_controller_block_unit|data_outl[3]"

Error: Net is fed by "msb:msb_controller_block_unit|data_outm[3]"