Wireless Transmission using Cyclone II FPGA (Verilog HDL)

module fifo

# (parameter B=8, W=4)

(clk, reset, read, write, write_data, read_data, empty, full);

input clk, reset, read, write;

input wire [B-1:0] write_data;

output empty, full;

output wire [B-1:0] read_data;

// signal declaration

reg [B-1:0] array_reg [2**W-1:0];

reg [W-1:0] write_reg, write_next, write_done;

reg [W-1:0] read_reg, read_next, read_done;

reg full_reg, empty_reg, full_next, empty_next;

wire write_enable;

// body

// register file write operation

always @(posedge clk)

if (write_enable)

array_reg[write_reg] <= write_data;

// register file read operation

assign read_data = array_reg[read_reg];

// write enabled only when FIFO is not full

assign write_enable = write & ~full_reg;

// fifo control logic

// register for read and write pointers

always @(posedge clk, posedge reset)

if (reset)

begin

write_reg <= 0;

read_reg <= 0;

full_reg <= 1'b0;

empty_reg <= 1'b1;

end

else

begin

write_reg <= write_next;

read_reg <= read_next;

full_reg <= full_next;

empty_reg <= empty_next;

end

// next-state logic for read and write pointers

always @*

begin

// successive pointer values

write_done = write_reg + 1;

read_done = read_reg + 1;

// default: keep old values

write_next = write_reg;

read_next = read_reg;

full_next = full_reg;

empty_next = empty_reg;

case ({write, read})

//2'b00: no options

2'b01: // read

if (~empty_reg)

begin

read_next = read_done;

full_next = 0;

if (read_done==write_reg)

empty_next = 1;

end

2'b10: // write

if (~full_reg)

begin

write_next = write_done;

empty_next = 0;

if (write_done==read_reg)

full_next = 1;

end

2'b11: //read and write

begin

write_next= write_done;

read_next = read_done;

end

endcase

end

// output

assign full = full_reg;

assign empty = empty_reg;

endmodule