Wireless Transmission using Cyclone II FPGA (Verilog HDL)

This is another example codings we've written:

module testing_wed2 (data_in, data_out);

input [7:0] data_in;

output wire [3:0] data_out;

reg lsb_enable;

wire msb_enable;

always@*

begin

if(data_in)

lsb_enable <= 1;

else

lsb_enable <= 0;

end

lsbmo lsbmo_controller_block_unit

(.data_inl(data_in),

.lsb_enable(lsb_enable),

.msb_enable(msb_enable),

.data_outl(data_out));

msb msb_controller_block_unit

(.data_inm(data_in),

.msb_enable(msb_enable),

.data_outm(data_out));

endmodule