Wireless Transmission using Cyclone II FPGA (Verilog HDL)

module lsbmo(

input [7:0] data_inl,

input lsb_enable,

output reg [3:0] data_outl ,

output reg msb_enable );

always@*

begin

if(lsb_enable)

data_outl = data_inl[3:0];

msb_enable <= 1;

end

endmodule

module msb(

input msb_enable,

input [7:0] data_inm,

output reg [3:0] data_outm

);

always@*

begin

if(msb_enable)

data_outm = data_inm [7:4];

end

endmodule

Error: Net "data_out[3]~0", which fans out to "data_out[3]", cannot be assigned more than one value

Error: Net is fed by "lsbmo:lsbmo_controller_block_unit|data_outl[3]"

Error: Net is fed by "msb:msb_controller_block_unit|data_outm[3]"