Wireless Transmission using Cyclone II FPGA (Verilog HDL)

RF frequency 433.92 MHz

Modulation: FSK

I'm connecting the 4 data pins of the decoder at the receiver side to 4 LEDs.

this is the code for receiver side:

module receive_testing

# (parameter W_SIZE = 2) // 2^W_SIZE word in FIFO

(clk, reset, from_expansion, LED);

input clk, reset;

input [3:0] from_expansion;

output wire [7:0] LED;

reg write_code;

wire full_code, read_code;

reg [7:0] data_out_reg;

wire write_enable, write_disable;

wire [7:0] data_out_next;

fifo# (.B(8), .W(W_SIZE)) fifo_block_unit

(.clk(clk),

.reset(reset),

.write(write_code),

.read(read_code),

.write_data(from_expansion),

.read_data(data_out_next),

.empty(write_enable),

.full());

always @(posedge clk)

if (reset)

data_out_reg = 0;

else

data_out_reg <= data_out_next;

always@*

begin

if(from_expansion)

write_code <= 1;

else

write_code <= 0;

end

assign LED = data_out_reg;

assign read_code = ~write_code;

endmodule