wire assignment in verilog

I check the Questasim user guide, I couldn't find an option on this warning message enabling. Since this question is more towards EDA, you may log a case to them to further clarify this. https://www.siemens.com/global/en.html, siemens now officially own questasim.

Any further question that you have?

Then, is there a setting that changes the initial value to x or z, not zero, for the unallocated top 8 bits as in the example above, not a warning message? I wonder how I can check this in the compile stage or in the simulation when the bit width is not correct. Because I automatically assigned 0 for the bit width that is not correct, and if I can't check it in the compile stage or in the simulation, I think this will come to a fatal problem later on.

Since this issue pertains to the usage of Questasim commands (TCL), we will need to consult the relevant team for assistance. I have attempted to find an answer in the Questasim user guide located at W:\24.3\linux\questa_fse\docs, but was unsuccessful. We will get back to you, but it may take some time(1 to 2 weeks). Thank you for your patience.

Hi,

I just get feedback from Mentor:

For the question regarding warning messages about the bit mismatch, there should be a vopt warning as the example below:

** Warning: (vopt-2241) Connection width does not match width of port 'data_in'. The port definition is at: dut.sv(3).

if you have vopt.log file generated? You may be able to search vopt-2241 and it should have bit-mismatch warning.

They have also consulted with R&D regarding the question on setting that changes the initial value to x or z, not zero.

According to R&D, currently by default:

Unconnected MSB of type reg will be 0, as this is considered as an assignment.

Unconnected MSB of type wire will be Z,

Let me know if the above help?

Thanks,

Is there any further question on this?

Thank you for your answer.
I have a question for your answer. For input, don't you write the wire type by default? If so, shouldn't the undefined top bits be allocated as Z? Also, I couldn't find a warning message like vopt-2241 even though the bit was not allocated properly (assign D[15:0] = {8{A}};) and the compilation went well. It seems like Modelsim automatically allocates 0 for the unallocated parts, am I right to understand?

I will get back to you with an answer by this week.

Please allow us some time to look into.

Thank you for your time and patience.

Regards,

Richard Tan

Hi, can you check your email for this? As this require long explanation from Questa support.