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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
junyoung2New Contributor
New ContributorThen, is there a setting that changes the initial value to x or z, not zero, for the unallocated top 8 bits as in the example above, not a warning message? I wonder how I can check this in the compile stage or in the simulation when the bit width is not correct. Because I automatically assigned 0 for the bit width that is not correct, and if I can't check it in the compile stage or in the simulation, I think this will come to a fatal problem later on.
