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junyoung2's avatar
junyoung2
Icon for New Contributor rankNew Contributor
1 year ago

wire assignment in verilog

Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
Hdl
Simulation
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Since this issue pertains to the usage of Questasim commands (TCL), we will need to consult the relevant team for assistance. I have attempted to find an answer in the Questasim user guide located at W:\24.3\linux\questa_fse\docs, but was unsuccessful. We will get back to you, but it may take some time(1 to 2 weeks). Thank you for your patience.