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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
junyoung2New Contributor
New ContributorThank you for your answer.
I have a question for your answer. For input, don't you write the wire type by default? If so, shouldn't the undefined top bits be allocated as Z? Also, I couldn't find a warning message like vopt-2241 even though the bit was not allocated properly (assign D[15:0] = {8{A}};) and the compilation went well. It seems like Modelsim automatically allocates 0 for the unallocated parts, am I right to understand?
