wire assignment in verilog

Hi,

I just get feedback from Mentor:

For the question regarding warning messages about the bit mismatch, there should be a vopt warning as the example below:

** Warning: (vopt-2241) Connection width does not match width of port 'data_in'. The port definition is at: dut.sv(3).

if you have vopt.log file generated? You may be able to search vopt-2241 and it should have bit-mismatch warning.

They have also consulted with R&D regarding the question on setting that changes the initial value to x or z, not zero.

According to R&D, currently by default:

Unconnected MSB of type reg will be 0, as this is considered as an assignment.

Unconnected MSB of type wire will be Z,

Let me know if the above help?

Thanks,