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Ruturaj_D_Intel's avatar
Ruturaj_D_Intel
Icon for New Contributor rankNew Contributor
6 years ago

Why transceiver links are not detected in Transceiver Toolkit?

I am using Arria 10 device and ​Quartus Prime Pro version 17.0. In order to tune and check quality of Transceiver links in my design I am using transceiver toolkit and followed the steps given in the training video. I did connect reconfig_clk and reconfig_reset mentioned in the video but in system console I see transceiver is detected but no information is populated for transceiver channels. I see a message which says "input clock is running, reset is not asserted" but do not what this means.

I have a question about reconfig_reset, is it active high or active low reset and what kind of reset needs to be connected to it? Are there any guidelines about connecting reconfig_clk and reconfig_reset?

I want to use auto sweep feature and have just connected reconfig_clk and reconfig_reset as mentioned in one of the videos.

I referred to below video, let me know if there is any better resource to refer than this video.

http://www.altera.com/customertraining/webex/Transceiver_Toolkit_A10/player.html

Adding screen shot of system console.

Thanks,

Ruturaj.

10 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Ruturaj, As I understand it, you have some inquiries related to using XCVR toolkit in A10 devices. In your observation, seems like the channels are not auto-populated. Would you mind to try with the following simple 1 channel design example from wiki which was previously verified working on an A10 devkit to see if it works for you? You may need to change the device, clock and XCVR frequency/pinout according to your board. https://fpgawiki.intel.com/wiki/Arria10_Transceiver_PHY_Basic_Design_Examples#Arria_10_Native_PHY_with_Transceiver_Toolkit_design_example Please let me know if there is any concern. Thank you. Best regards, Chee Pin
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Ruturaj, Regarding your inquiry on the reconfig_reset, it is an active high input. For the reconfig_clk, you would need to ensure it is directly sourced from a free-running clock source ie oscillator on-board and stable prior to FPGA configuration. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Ruturaj, Just would like to follow up with you on this. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
    • Ruturaj_D_Intel's avatar
      Ruturaj_D_Intel
      Icon for New Contributor rankNew Contributor
      6 years ago
      Hi Chee Pin, Thank you for pointing to example design. I did take a look at the example design and could compile it, but I do not think I will be able to test example design on board we have. I am not sure if it is safe to test on the board. After studying example design I added in-system probes and debug IP in my design to control reconfig_reset and reset of XCVR link. Reconfig_clk is free running clock of 100 MHz. But even after these modifications and controlling reset from in-system sources and probes editor XCVR toolkit still does not populate XCVR links. I still see the message “Input clock is running, reset is not asserted”; I would like to know what this message mean? I am not sure if I am missing any step. In my design x1 XCVR channel is instantiated 4 times and I do not configure native phy as x4 link directly, due to this even though design has x4 links system console only shows 1 link as shown in the uploaded snap shot. Thanks, Ruturaj.
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Ruturaj, Thanks for your update. By merely looking at the “Input clock is running, reset is not asserted” message, I believe it is indicating that clock is present and reset is OK. Which indirectly indicate that the channels should be in user mode. Based on the current observation, I am unable to tell what might be the problem on your side. I would recommend you to try out the example design from wiki. Alternatively, you may try to create a simple one channel test design mimic the example design if you have concern running the example design. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
  • Justin_R_Intel's avatar
    Justin_R_Intel
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi Chee Pin,

    I am also working with Ruturaj on this. We are using a MCP where the Arria 10 is programmed by the CPU. We aren't able to test out the simple design without rewriting all of our IO constraints. Since we are all at Intel, would you be able to meet online? I believe we have a very custom setup.

    Thanks,

    Justin

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Justin, thanks for your update. I have dropped you an email and we shall continue to follow up from there. Thank you.
  • TomCarpenter's avatar
    TomCarpenter
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    So I'm having exactly the same issue is Quartus Standard 22.1 with the Transceiver Toolkit trying to check the status of transceivers in the JESD204 IP core (configured for recieve only). I've enabled the various parameters necessary to enable the debug master endpoint:

    But after compiling and running, no links are shown in transciever toolkit. I just get a blank screen. I can see `phy_0` in the system explorer, which I assume means that the endpoints are correctly set up (I haven't specifically connected thte reconfig interface to a JTAG master as I believe that's what the "Altera Debug Master Endpoint" bit is for). I get the same "input clock is running, reset not asserted" tooltip on the PHY.

    I note that this thread is 4 years old. Did you actually find any resolution to this? Could you post any details from your "meeting online"?

    I can't use the example designs because this is not the Arria 10 GX development kit, but rather another SoM product using an Arria 10. But comparing the entity list from the compiled example project, and my project, both seem to have the same contents. The JTAG ADME core is there.

    I mean, I'm sure all of you being intel employees is great for you to be able to go offline and have an internal meeting to resolve it, but does absolutely nothing to help your customers who have paid for your products.

    • TomCarpenter's avatar
      TomCarpenter
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      So the only way I could get this working is to manually re-enable all of the ODI Soft Logic parameter code which was commented out and disabled by Altera at some point around Quartus 16

      1. Modifying the JESD core TCL files to find any reference to `set_odi_soft_logic_enable` or similar and uncomment them

      2. Add the following to a `quartus.ini` file in the project directory:

      altera_xcvr_native_a10_enable_odi_acc=on
      altera_xcvr_native_a10_debug=on
      altera_xcvr_native_a10_advanced=on
      altera_xcvr_avmm_a10_advanced=on

      After that regenerate the HDL for Platform Design, recompile, and voila:

    • David32's avatar
      David32
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      Hello all,

      I am having a similar problem.

      Trying to debug a JESD IP (receiver only).

      I have enabled all the options such as dynamic reconfiguration and connected a JTAG Master.

      The System Console does not even recognize any debug endpoint, even though the JTAG Master is recognized in the console.

      Any help would be much appreciated.

      (we PAID good money for the JESD IP).

      Thanks

      David