Forum Discussion
CheepinC_altera
Regular Contributor
6 years agoHi Ruturaj,
Just would like to follow up with you on this.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Ruturaj_D_Intel
New Contributor
6 years agoHi Chee Pin,
Thank you for pointing to example design. I did take a look at the example design and could compile it, but I do not think I will be able to test example design on board we have. I am not sure if it is safe to test on the board.
After studying example design I added in-system probes and debug IP in my design to control reconfig_reset and reset of XCVR link. Reconfig_clk is free running clock of 100 MHz. But even after these modifications and controlling reset from in-system sources and probes editor XCVR toolkit still does not populate XCVR links.
I still see the message “Input clock is running, reset is not asserted”; I would like to know what this message mean?
I am not sure if I am missing any step.
In my design x1 XCVR channel is instantiated 4 times and I do not configure native phy as x4 link directly, due to this even though design has x4 links system console only shows 1 link as shown in the uploaded snap shot.
Thanks,
Ruturaj.