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Altera_Forum's avatar
Altera_Forum
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14 years ago

Which one is the right design??(very simple design)

please i need yours help.

in the following design the result was calculated by the signal (x) and connected to the output port (output),

i got the following result:

lut =17

worst-case tsu = 4.8ns

worst-case tco = 8.5

worst-case th = -1.1ns

library ieee;

use ieee.std_logic_1164.all;

entity test is

port( clk : in std_logic;

rst : in std_logic;

input : in std_logic_vector (7 downto 0);

output : out std_logic_vector (7 downto 0));

end entity test;

architecture kkk of test is

signal x : std_logic_vector (7 downto 0);

signal q : std_logic_vector (7 downto 0);

begin

q <= input;

process (clk,rst)

begin

if (rst='1') then

x <= "00000000";

elsif (clk'event and clk='1') then

x(0) <= q(7) AND q(6) AND q(4) AND q(3) AND q(1) AND q(0) ;

x(1) <= q(4) AND q(2) ;

x(2) <= q(5) AND q(0) ;

x(3) <= q(4) AND q(2) ;

x(4) <= q(7) AND q(5) ;

x(5) <= q(7) AND q(5) AND q(4) AND q(1) ;

x(6) <= q(5) AND q(3) AND q(0) ;

x(7) <= q(5) AND q(3) AND q(1) AND q(0) ;

output <= x ;

end if;

end process;

end architecture kkk;

while in the following design i used the output port directly.

i got:

lut =9

worst-case tsu = 5 ns

worst-case tco = 8.8 ns

worst-case th = -0.7 ns

library ieee;

use ieee.std_logic_1164.all;

entity test is

port( clk : in std_logic;

rst : in std_logic;

input : in std_logic_vector (7 downto 0);

output : out std_logic_vector (7 downto 0));

end entity test;

architecture kkk of test is

signal q : std_logic_vector (7 downto 0);

begin

q <= input;

process (clk,rst)

begin

if (rst='1') then

output <= "00000000";

elsif (clk'event and clk='1') then

output(0) <= q(7) AND q(6) AND q(4) AND q(3) AND q(1) AND q(0) ;

output(1) <= q(4) AND q(2) ;

output(2) <= q(5) AND q(0) ;

output(3) <= q(4) AND q(2) ;

output(4) <= q(7) AND q(5) ;

output(5) <= q(7) AND q(5) AND q(4) AND q(1) ;

output(6) <= q(5) AND q(3) AND q(0) ;

output(7) <= q(5) AND q(3) AND q(1) AND q(0) ;

end if;

end process;

end architecture kkk;

thanks in advance

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    In the first one you are using intermediate signal x then registering the output from x.

    In the second one you register output directly thus eliminating 8 registers between x and output.

    Both are correct functionally but I don't quite get your timing report. The second one should be enough unless - in a large project you get timing violations and may opt for extra registers.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for reply,

    I prefer the second one because of less LUT.

    do you know please how to calculate the critical path delay CPD for the design and Maximum frequency that the design can work?

    the first design gave me the follwoing result:

    Clock Setup 'clk' = Restricted to 166.67 MHz (period = 6 ns)

    while the secound design did not gave information about the clock Setup 'clk'
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The compiler will tell you fmax (you don't need to calculate it). In the first case it gave you because there are 8 paths of direct connection between x and output.

    In the second case there is no path to analyse between two registers.

    Normally, all io inputs/outputs must be registered by user and all internal modules can be registered at outputs only since the internal inputs acquire

    registers from outputs of previous module.

    So you need to register the input, i.e. just insert your "q <= input" inside clocked process. so you are back to 8 more registers I am afraid. But when this module is part of longer chain of modules then you don't need to register the input.

    You need to tell compiler what is your clock speed in the timing settings.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I do not know how to inserting "q<= input" inside clocked process!!

    But in case of get more register, then I thinks is better to used the first design.

    About the first design, fmax is alwase constant value even when I used another design with 64-bit "input" and "output" with alot of XOR between qs!!

    I think fmax is not for all the design, it is just for the registers x and output only.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    the fmax reported is just for the direct wires between x and output as you concluded.

    For any module design, the tool cannot check the speed from unregistered inputs. Thus your first design will give false results.

    You need to "temporarily" register the inputs so that the tool will check the more important paths between input and output. If then you add the work to a project that will register your input from front module then you can remove input registers.

    for registering your input just pull your statement q <= input and put after clock edge statement.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I should have said fmax is for output registers only(not x registers and does not apply to gating logic infront of x up to inputs)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thank you so much for helping, know I am understand your idea about temporarily register the inputs, can you please give me more details, I mean the step of temporarily register the inputs since I am new in Quartus tool.

    Thanks Kaz
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    
begin
--q <= input; -- comment in if in project
  
process (clk,rst)  
  begin
  
    if  (rst='1') then
           output <= "00000000";    
     elsif (clk'event and clk='1') then
   q <= input; -- comment out if in project
    
       output(0)  <=  q(7)  AND q(6) AND q(4) AND q(3) AND q(1) AND q(0)  ; 
       output(1)  <=  q(4)  AND q(2)   ;
       output(2)  <=  q(5)  AND q(0)   ;
       output(3)  <=  q(4)  AND q(2)   ; 
       output(4)  <=  q(7)  AND q(5)   ;
       output(5)  <=  q(7)  AND q(5) AND q(4) AND q(1)  ;
       output(6)  <=  q(5)  AND q(3) AND q(0)  ;
       output(7)  <=  q(5)  AND q(3) AND q(1) AND q(0)  ;
    end if;
  end process;
end architecture kkk;

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ok thanks, I recompiled the design with the new change, as you expected, LUT increased to 18 and:

    Clock Setup 'clk' = Restricted to 166.67 MHz (period = 6 ns).