Which one is the right design??(very simple design)

the fmax reported is just for the direct wires between x and output as you concluded.

For any module design, the tool cannot check the speed from unregistered inputs. Thus your first design will give false results.

You need to "temporarily" register the inputs so that the tool will check the more important paths between input and output. If then you add the work to a project that will register your input from front module then you can remove input registers.

for registering your input just pull your statement q <= input and put after clock edge statement.