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Altera_Forum's avatar
Altera_Forum
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14 years ago

Which one is the right design??(very simple design)

please i need yours help. in the following design the result was calculated by the signal (x) and connected to the output port (output), i got the following result: lut =17 worst-case tsu ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok thanks, I recompiled the design with the new change, as you expected, LUT increased to 18 and:

Clock Setup 'clk' = Restricted to 166.67 MHz (period = 6 ns).