Which one is the right design??(very simple design)

Thanks for reply,

I prefer the second one because of less LUT.

do you know please how to calculate the critical path delay CPD for the design and Maximum frequency that the design can work?

the first design gave me the follwoing result:

Clock Setup 'clk' = Restricted to 166.67 MHz (period = 6 ns)

while the secound design did not gave information about the clock Setup 'clk'