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Altera_Forum's avatar
Altera_Forum
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14 years ago

Which one is the right design??(very simple design)

please i need yours help. in the following design the result was calculated by the signal (x) and connected to the output port (output), i got the following result: lut =17 worst-case tsu ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I do not know how to inserting "q<= input" inside clocked process!!

But in case of get more register, then I thinks is better to used the first design.

About the first design, fmax is alwase constant value even when I used another design with 64-bit "input" and "output" with alot of XOR between qs!!

I think fmax is not for all the design, it is just for the registers x and output only.