What data types can be synthesis in VHDL

Hi,

supported data types are listed in QII Help, referring to common VHDL standard libraries. Assuming you use IEEE.numeric.std, the data types are listed e.g. in http://www.csee.umbc.edu/portal/help/vhdl/numeric_std.vhdl.

Thus you can assign (to the 8Bit vector) either binary "10101010", hexadecimal x"AA" or octal (something I never seen any practical implementation so far).

The double quotes are VHDL syntax - that's why you have to use them... :-)

Additionally the std_logic_vector is just a "collection of bits" - if you intend to do arithmetics or comparisons, you have to be careful about the MSB (being MSB of value or sign). Thus in numeric_std your's Q would be defined as q : signed(7 downto 0) with MSB = sign or q : unsigned(7 downto 0) with MSB = MSB...

If you want to assign a decimal, you have to use a type conversion function to specify the decimal value "98" being a integer and to initialize the conversion in 8Bit Binary, i.e.

q <= std_logic_vector(98)

q <= signed(98)

q <= unsigned(98)

depending on definition of "q"...

And well.. as VHDL describes real hardware, thus binary representations reflect hardware realization best, while decimal integers are the numbers humans are used to... :-)

Contrary to some other languages there is less "implicit type conversion" implemented in VHDL. On first hand this may be annoying as you need to do more typing but to be honest this prevents the common mismatch between your intended definition and the "compiler's good guess" what might have been your intention.

While the interpretation is normally written in the messages, do you really read carefully all messages and check, if the "good guess" matches your intention..?

You simply need to use VHDL-2008.

Q <= 8D"98";

will work just fine.

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I read VHDL tutorial but are confused in some data types. I found there are a lot of data types in VHDL, it is not easy to remember all of them.

I think only some of them are commonly used, these can be sythesised, will be most important. So I wonder anyone can give a small conclusion:

1. What are commonly used data types in VHDL?

2. What data types can be sythesised?

I have another question is what format can I assign value to STD_LOGIC_Vector? I try it in Quartus, if I define:

Q : buffer STD_LOGIC_Vector (7 downto 0);

I can only assign value to it like:

Q<=B"1000_0000";

Q<=X"AA";

Why do I have to use double quotes? I even can't assign it with decimal, if I wrote as:

Q<="98";

It reports error, how can I assign it with decimal&#65311;

Thanks very much.

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Thanks, both of you. But I found another thing in my following code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity signed_adder is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

Q : buffer STD_LOGIC_Vector (7 downto 0)); -- signed

end signed_adder;

architecture Behavioral of signed_adder is

SIGNAL temp : STD_LOGIC_VECTOR (7 downto 0);

begin

temp<=X"15";

process (clk)

begin

if clk'event and clk='1' then

if (rst='1') then

Q<=8D"12";

else

Q<=Q+1;

end if;

end if;

--Q<=temp;

end process;

end Behavioral;

Why in the code"Q<=Q+1;", It can work that 1 without double quote?

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Another question I have is: if I assign a value to a signal, variable, or port, does the value have to have double quote no matter what type they are?

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I wrote some code below, in the spirit of VHDL-2008 and defining the constant in an easier way. To explicitly answer your question, if you use std_logic_vector, unsigned, or signed type, you need to explicitly use double quotes in defining the constant value in VHDL. This is part of the VHDL language specification.

The code below uses integer. The definition of the constant is simple.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity signed_adder is 
Port (
     clk   :   in std_logic;
      rst   :   in std_logic;
      Q     :   out std_logic_vector(7 downto 0)
      );
      
architecture RTL of signed_adder is 
signal   qx : integer range 0 to 255;
CONSTANT resetValue := integer := 12;
begin
process(all) begin
   if rst then
      qx <= 12;
    elsif rising_edge(clk) then
      qx <= qx + 1;
    end if;
end process;
Q <= std_logic_vector(to_signed(qx,8));
end RTL;

Without referring to VHDL 2008 features, a good VHDL coding style might look like this

- don't use legacy libraries STD_LOGIC_UNSIGNED or STD_LOGIC_SIGNED

- use numeric data types signed and unsigned for variables/signals involving numeric operations

- you can use to_signed() respectively to_unsigned() functions to assign integer values or expressions to signed/unsigned

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Why in the code"Q<=Q+1;", It can work that 1 without double quote?

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In some signed/unsigned expressions, integer values can be used directly, because the operators are defined respectively. If you're interested in the details, review the library code under "quartus\libraries\vhdl\ieee".