What data types can be synthesis in VHDL

Thanks, both of you. But I found another thing in my following code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity signed_adder is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

Q : buffer STD_LOGIC_Vector (7 downto 0)); -- signed

end signed_adder;

architecture Behavioral of signed_adder is

SIGNAL temp : STD_LOGIC_VECTOR (7 downto 0);

begin

temp<=X"15";

process (clk)

begin

if clk'event and clk='1' then

if (rst='1') then

Q<=8D"12";

else

Q<=Q+1;

end if;

end if;

--Q<=temp;

end process;

end Behavioral;

Why in the code"Q<=Q+1;", It can work that 1 without double quote?