What data types can be synthesis in VHDL

Without referring to VHDL 2008 features, a good VHDL coding style might look like this

- don't use legacy libraries STD_LOGIC_UNSIGNED or STD_LOGIC_SIGNED

- use numeric data types signed and unsigned for variables/signals involving numeric operations

- you can use to_signed() respectively to_unsigned() functions to assign integer values or expressions to signed/unsigned

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Why in the code"Q<=Q+1;", It can work that 1 without double quote?

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In some signed/unsigned expressions, integer values can be used directly, because the operators are defined respectively. If you're interested in the details, review the library code under "quartus\libraries\vhdl\ieee".